forked from OSchip/llvm-project
parent
7020f255b1
commit
d089a43de4
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@ -1414,20 +1414,19 @@ void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
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uint64_t Val) const {
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uint64_t Val) const {
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checkUInt<32>(Val, Type);
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checkUInt<32>(Val, Type);
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uint32_t Inst = read32le(Loc);
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uint32_t NewInst;
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if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
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if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
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// Generate movz.
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// Generate MOVZ.
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unsigned RegNo = (Inst & 0x1f);
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uint32_t RegNo = read32le(Loc) & 0x1f;
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NewInst = (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5);
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write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
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} else if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
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return;
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// Generate movk
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unsigned RegNo = (Inst & 0x1f);
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NewInst = (0xf2800000 | RegNo) | ((Val & 0xffff) << 5);
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} else {
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llvm_unreachable("invalid Relocation for TLS IE to LE Relax");
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}
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}
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write32le(Loc, NewInst);
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if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
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// Generate MOVK.
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uint32_t RegNo = read32le(Loc) & 0x1f;
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write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
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return;
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}
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llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
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}
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}
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// Implementing relocations for AMDGPU is low priority since most
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// Implementing relocations for AMDGPU is low priority since most
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