forked from OSchip/llvm-project
Encode alignment attribute for `atomicrmw`
This is a follow up patch to D83136 adding the align attribute to `atomicwmw`. Differential Revision: https://reviews.llvm.org/D83465
This commit is contained in:
Guillaume Chatelet
James Y Knight
parent
cb41ee92da
commit
d06ab79816
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@ -9701,7 +9701,7 @@ Syntax:
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::
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atomicrmw [volatile] <operation> <ty>* <pointer>, <ty> <value> [syncscope("<target-scope>")] <ordering> ; yields ty
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atomicrmw [volatile] <operation> <ty>* <pointer>, <ty> <value> [syncscope("<target-scope>")] <ordering>[, align <alignment>] ; yields ty
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Overview:
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"""""""""
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@ -9739,6 +9739,13 @@ the ``atomicrmw`` is marked as ``volatile``, then the optimizer is not
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allowed to modify the number or order of execution of this
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``atomicrmw`` with other :ref:`volatile operations <volatile>`.
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The instruction can take an optional ``align`` attribute.
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The alignment must be a power of two greater or equal to the size of the
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`<value>` type. If unspecified, the alignment is assumed to be equal to the
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size of the '<value>' type. Note that this default alignment assumption is
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different from the alignment used for the load/store instructions when align
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isn't specified.
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A ``atomicrmw`` instruction can also take an optional
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":ref:`syncscope <syncscope>`" argument.
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@ -9759,10 +9766,8 @@ operation argument:
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- xor: ``*ptr = *ptr ^ val``
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- max: ``*ptr = *ptr > val ? *ptr : val`` (using a signed comparison)
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- min: ``*ptr = *ptr < val ? *ptr : val`` (using a signed comparison)
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- umax: ``*ptr = *ptr > val ? *ptr : val`` (using an unsigned
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comparison)
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- umin: ``*ptr = *ptr < val ? *ptr : val`` (using an unsigned
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comparison)
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- umax: ``*ptr = *ptr > val ? *ptr : val`` (using an unsigned comparison)
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- umin: ``*ptr = *ptr < val ? *ptr : val`` (using an unsigned comparison)
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- fadd: ``*ptr = *ptr + val`` (using floating point arithmetic)
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- fsub: ``*ptr = *ptr - val`` (using floating point arithmetic)
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@ -7499,6 +7499,7 @@ int LLParser::parseAtomicRMW(Instruction *&Inst, PerFunctionState &PFS) {
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bool isVolatile = false;
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bool IsFP = false;
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AtomicRMWInst::BinOp Operation;
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MaybeAlign Alignment;
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if (EatIfPresent(lltok::kw_volatile))
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isVolatile = true;
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@ -7531,7 +7532,8 @@ int LLParser::parseAtomicRMW(Instruction *&Inst, PerFunctionState &PFS) {
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if (parseTypeAndValue(Ptr, PtrLoc, PFS) ||
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parseToken(lltok::comma, "expected ',' after atomicrmw address") ||
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parseTypeAndValue(Val, ValLoc, PFS) ||
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parseScopeAndOrdering(true /*Always atomic*/, SSID, Ordering))
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parseScopeAndOrdering(true /*Always atomic*/, SSID, Ordering) ||
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parseOptionalCommaAlign(Alignment, AteExtraComma))
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return true;
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if (Ordering == AtomicOrdering::Unordered)
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@ -7566,11 +7568,12 @@ int LLParser::parseAtomicRMW(Instruction *&Inst, PerFunctionState &PFS) {
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if (Size < 8 || (Size & (Size - 1)))
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return error(ValLoc, "atomicrmw operand must be power-of-two byte-sized"
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" integer");
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Align Alignment(
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const Align DefaultAlignment(
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PFS.getFunction().getParent()->getDataLayout().getTypeStoreSize(
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Val->getType()));
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AtomicRMWInst *RMWI =
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new AtomicRMWInst(Operation, Ptr, Val, Alignment, Ordering, SSID);
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new AtomicRMWInst(Operation, Ptr, Val,
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Alignment.getValueOr(DefaultAlignment), Ordering, SSID);
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RMWI->setVolatile(isVolatile);
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Inst = RMWI;
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return AteExtraComma ? InstExtraComma : InstNormal;
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@ -5131,29 +5131,55 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
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break;
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}
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case bitc::FUNC_CODE_INST_ATOMICRMW: {
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// ATOMICRMW:[ptrty, ptr, val, op, vol, ordering, ssid]
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// ATOMICRMW:[ptrty, ptr, val, op, vol, ordering, ssid, align?]
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const size_t NumRecords = Record.size();
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unsigned OpNum = 0;
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Value *Ptr, *Val;
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if (getValueTypePair(Record, OpNum, NextValueNo, Ptr, &FullTy) ||
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!isa<PointerType>(Ptr->getType()) ||
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popValue(Record, OpNum, NextValueNo,
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getPointerElementFlatType(FullTy), Val) ||
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OpNum + 4 != Record.size())
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Value *Ptr = nullptr;
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if (getValueTypePair(Record, OpNum, NextValueNo, Ptr, &FullTy))
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return error("Invalid record");
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AtomicRMWInst::BinOp Operation = getDecodedRMWOperation(Record[OpNum]);
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if (!isa<PointerType>(Ptr->getType()))
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return error("Invalid record");
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Value *Val = nullptr;
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if (popValue(Record, OpNum, NextValueNo,
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getPointerElementFlatType(FullTy), Val))
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return error("Invalid record");
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if (!(NumRecords == (OpNum + 4) || NumRecords == (OpNum + 5)))
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return error("Invalid record");
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const AtomicRMWInst::BinOp Operation =
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getDecodedRMWOperation(Record[OpNum]);
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if (Operation < AtomicRMWInst::FIRST_BINOP ||
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Operation > AtomicRMWInst::LAST_BINOP)
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return error("Invalid record");
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AtomicOrdering Ordering = getDecodedOrdering(Record[OpNum + 2]);
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const bool IsVol = Record[OpNum + 1];
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const AtomicOrdering Ordering = getDecodedOrdering(Record[OpNum + 2]);
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if (Ordering == AtomicOrdering::NotAtomic ||
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Ordering == AtomicOrdering::Unordered)
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return error("Invalid record");
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SyncScope::ID SSID = getDecodedSyncScopeID(Record[OpNum + 3]);
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Align Alignment(
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TheModule->getDataLayout().getTypeStoreSize(Val->getType()));
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I = new AtomicRMWInst(Operation, Ptr, Val, Alignment, Ordering, SSID);
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const SyncScope::ID SSID = getDecodedSyncScopeID(Record[OpNum + 3]);
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MaybeAlign Alignment;
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if (NumRecords == (OpNum + 5)) {
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if (Error Err = parseAlignmentValue(Record[6], Alignment))
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return Err;
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}
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if (!Alignment)
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Alignment =
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Align(TheModule->getDataLayout().getTypeStoreSize(Val->getType()));
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I = new AtomicRMWInst(Operation, Ptr, Val, *Alignment, Ordering, SSID);
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FullTy = getPointerElementFlatType(FullTy);
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cast<AtomicRMWInst>(I)->setVolatile(Record[OpNum+1]);
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cast<AtomicRMWInst>(I)->setVolatile(IsVol);
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InstructionList.push_back(I);
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break;
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}
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@ -3071,6 +3071,7 @@ void ModuleBitcodeWriter::writeInstruction(const Instruction &I,
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Vals.push_back(getEncodedOrdering(cast<AtomicRMWInst>(I).getOrdering()));
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Vals.push_back(
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getEncodedSyncScopeID(cast<AtomicRMWInst>(I).getSyncScopeID()));
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Vals.push_back(getEncodedAlign(cast<AtomicRMWInst>(I).getAlign()));
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break;
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case Instruction::Fence:
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Code = bitc::FUNC_CODE_INST_FENCE;
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@ -4327,6 +4327,7 @@ void AssemblyWriter::printInstruction(const Instruction &I) {
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} else if (const AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(&I)) {
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writeAtomic(RMWI->getContext(), RMWI->getOrdering(),
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RMWI->getSyncScopeID());
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Out << ", align " << RMWI->getAlign().value();
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} else if (const FenceInst *FI = dyn_cast<FenceInst>(&I)) {
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writeAtomic(FI->getContext(), FI->getOrdering(), FI->getSyncScopeID());
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} else if (const ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(&I)) {
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@ -734,28 +734,55 @@ define void @atomics(i32* %word) {
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; CHECK: %cmpxchg.6 = cmpxchg volatile i32* %word, i32 0, i32 10 seq_cst monotonic
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%cmpxchg.7 = cmpxchg weak volatile i32* %word, i32 0, i32 11 syncscope("singlethread") seq_cst monotonic
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; CHECK: %cmpxchg.7 = cmpxchg weak volatile i32* %word, i32 0, i32 11 syncscope("singlethread") seq_cst monotonic
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%atomicrmw.xchg = atomicrmw xchg i32* %word, i32 12 monotonic
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; CHECK: %atomicrmw.xchg = atomicrmw xchg i32* %word, i32 12 monotonic
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%atomicrmw.add = atomicrmw add i32* %word, i32 13 monotonic
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; CHECK: %atomicrmw.add = atomicrmw add i32* %word, i32 13 monotonic
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%atomicrmw.sub = atomicrmw sub i32* %word, i32 14 monotonic
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; CHECK: %atomicrmw.sub = atomicrmw sub i32* %word, i32 14 monotonic
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%atomicrmw.and = atomicrmw and i32* %word, i32 15 monotonic
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; CHECK: %atomicrmw.and = atomicrmw and i32* %word, i32 15 monotonic
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%atomicrmw.nand = atomicrmw nand i32* %word, i32 16 monotonic
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; CHECK: %atomicrmw.nand = atomicrmw nand i32* %word, i32 16 monotonic
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%atomicrmw.or = atomicrmw or i32* %word, i32 17 monotonic
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; CHECK: %atomicrmw.or = atomicrmw or i32* %word, i32 17 monotonic
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%atomicrmw.xor = atomicrmw xor i32* %word, i32 18 monotonic
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; CHECK: %atomicrmw.xor = atomicrmw xor i32* %word, i32 18 monotonic
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%atomicrmw.max = atomicrmw max i32* %word, i32 19 monotonic
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; CHECK: %atomicrmw.max = atomicrmw max i32* %word, i32 19 monotonic
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%atomicrmw.min = atomicrmw volatile min i32* %word, i32 20 monotonic
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; CHECK: %atomicrmw.min = atomicrmw volatile min i32* %word, i32 20 monotonic
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%atomicrmw.umax = atomicrmw umax i32* %word, i32 21 syncscope("singlethread") monotonic
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; CHECK: %atomicrmw.umax = atomicrmw umax i32* %word, i32 21 syncscope("singlethread") monotonic
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%atomicrmw.umin = atomicrmw volatile umin i32* %word, i32 22 syncscope("singlethread") monotonic
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; CHECK: %atomicrmw.umin = atomicrmw volatile umin i32* %word, i32 22 syncscope("singlethread") monotonic
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;; Atomic w/o alignment
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%atomicrmw_no_align.xchg = atomicrmw xchg i32* %word, i32 12 monotonic
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; CHECK: %atomicrmw_no_align.xchg = atomicrmw xchg i32* %word, i32 12 monotonic
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%atomicrmw_no_align.add = atomicrmw add i32* %word, i32 13 monotonic
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; CHECK: %atomicrmw_no_align.add = atomicrmw add i32* %word, i32 13 monotonic
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%atomicrmw_no_align.sub = atomicrmw sub i32* %word, i32 14 monotonic
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; CHECK: %atomicrmw_no_align.sub = atomicrmw sub i32* %word, i32 14 monotonic
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%atomicrmw_no_align.and = atomicrmw and i32* %word, i32 15 monotonic
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; CHECK: %atomicrmw_no_align.and = atomicrmw and i32* %word, i32 15 monotonic
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%atomicrmw_no_align.nand = atomicrmw nand i32* %word, i32 16 monotonic
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; CHECK: %atomicrmw_no_align.nand = atomicrmw nand i32* %word, i32 16 monotonic
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%atomicrmw_no_align.or = atomicrmw or i32* %word, i32 17 monotonic
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; CHECK: %atomicrmw_no_align.or = atomicrmw or i32* %word, i32 17 monotonic
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%atomicrmw_no_align.xor = atomicrmw xor i32* %word, i32 18 monotonic
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; CHECK: %atomicrmw_no_align.xor = atomicrmw xor i32* %word, i32 18 monotonic
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%atomicrmw_no_align.max = atomicrmw max i32* %word, i32 19 monotonic
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; CHECK: %atomicrmw_no_align.max = atomicrmw max i32* %word, i32 19 monotonic
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%atomicrmw_no_align.min = atomicrmw volatile min i32* %word, i32 20 monotonic
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; CHECK: %atomicrmw_no_align.min = atomicrmw volatile min i32* %word, i32 20 monotonic
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%atomicrmw_no_align.umax = atomicrmw umax i32* %word, i32 21 syncscope("singlethread") monotonic
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; CHECK: %atomicrmw_no_align.umax = atomicrmw umax i32* %word, i32 21 syncscope("singlethread") monotonic
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%atomicrmw_no_align.umin = atomicrmw volatile umin i32* %word, i32 22 syncscope("singlethread") monotonic
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; CHECK: %atomicrmw_no_align.umin = atomicrmw volatile umin i32* %word, i32 22 syncscope("singlethread") monotonic
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;; Atomic w/ alignment
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%atomicrmw.xchg = atomicrmw xchg i32* %word, i32 12 monotonic, align 16
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; CHECK: %atomicrmw.xchg = atomicrmw xchg i32* %word, i32 12 monotonic, align 16
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%atomicrmw.add = atomicrmw add i32* %word, i32 13 monotonic, align 16
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; CHECK: %atomicrmw.add = atomicrmw add i32* %word, i32 13 monotonic, align 16
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%atomicrmw.sub = atomicrmw sub i32* %word, i32 14 monotonic, align 16
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; CHECK: %atomicrmw.sub = atomicrmw sub i32* %word, i32 14 monotonic, align 16
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%atomicrmw.and = atomicrmw and i32* %word, i32 15 monotonic, align 16
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; CHECK: %atomicrmw.and = atomicrmw and i32* %word, i32 15 monotonic, align 16
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%atomicrmw.nand = atomicrmw nand i32* %word, i32 16 monotonic, align 16
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; CHECK: %atomicrmw.nand = atomicrmw nand i32* %word, i32 16 monotonic, align 16
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%atomicrmw.or = atomicrmw or i32* %word, i32 17 monotonic, align 16
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; CHECK: %atomicrmw.or = atomicrmw or i32* %word, i32 17 monotonic, align 16
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%atomicrmw.xor = atomicrmw xor i32* %word, i32 18 monotonic, align 16
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; CHECK: %atomicrmw.xor = atomicrmw xor i32* %word, i32 18 monotonic, align 16
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%atomicrmw.max = atomicrmw max i32* %word, i32 19 monotonic, align 16
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; CHECK: %atomicrmw.max = atomicrmw max i32* %word, i32 19 monotonic, align 16
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%atomicrmw.min = atomicrmw volatile min i32* %word, i32 20 monotonic, align 16
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; CHECK: %atomicrmw.min = atomicrmw volatile min i32* %word, i32 20 monotonic, align 16
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%atomicrmw.umax = atomicrmw umax i32* %word, i32 21 syncscope("singlethread") monotonic, align 16
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; CHECK: %atomicrmw.umax = atomicrmw umax i32* %word, i32 21 syncscope("singlethread") monotonic, align 16
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%atomicrmw.umin = atomicrmw volatile umin i32* %word, i32 22 syncscope("singlethread") monotonic, align 16
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; CHECK: %atomicrmw.umin = atomicrmw volatile umin i32* %word, i32 22 syncscope("singlethread") monotonic, align 16
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fence acquire
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; CHECK: fence acquire
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fence release
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@ -4,7 +4,7 @@
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; CHECK-LABEL: void @empty()
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; CHECK-NEXT: entry:
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; CHECK-NEXT: %0 = atomicrmw add i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0), i64 1 monotonic, !dbg [[DBG:![0-9]+]]
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; CHECK-NEXT: %0 = atomicrmw add i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0), i64 1 monotonic, align 8, !dbg [[DBG:![0-9]+]]
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; CHECK-NEXT: ret void, !dbg [[DBG]]
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define dso_local void @empty() !dbg !5 {
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