[x86] Distinguish the 'o', 'v', 'X', and 'i' inline assembly memory constraints.

Summary:
But still handle them the same way since I don't know how they differ on
this target.

Of these, 'o' and 'v' are not tested but were already implemented.

I'm not sure why 'i' is required for X86 since it's supposed to be an
immediate constraint rather than a memory constraint. A test asserts
without it so I've included it for now.

No functional change intended.

Reviewers: nadav

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8254

llvm-svn: 237517
This commit is contained in:
Daniel Sanders 2015-05-16 12:09:54 +00:00
parent 6fd0cb584a
commit d049669546
3 changed files with 17 additions and 3 deletions

View File

@ -248,6 +248,7 @@ public:
Constraint_R,
Constraint_S,
Constraint_T,
Constraint_X,
Constraint_Z,
Constraint_ZC,
Constraint_Zy,

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@ -2877,10 +2877,16 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
std::vector<SDValue> &OutOps) {
SDValue Op0, Op1, Op2, Op3, Op4;
switch (ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
case InlineAsm::Constraint_i:
// FIXME: It seems strange that 'i' is needed here since it's supposed to
// be an immediate and not a memory constraint.
// Fallthrough.
case InlineAsm::Constraint_o: // offsetable ??
case InlineAsm::Constraint_v: // not offsetable ??
default: return true;
case InlineAsm::Constraint_m: // memory
case InlineAsm::Constraint_X:
if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
return true;
break;

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@ -704,8 +704,15 @@ namespace llvm {
unsigned getInlineAsmMemConstraint(
const std::string &ConstraintCode) const override {
// FIXME: Map different constraints differently.
return InlineAsm::Constraint_m;
if (ConstraintCode == "i")
return InlineAsm::Constraint_i;
else if (ConstraintCode == "o")
return InlineAsm::Constraint_o;
else if (ConstraintCode == "v")
return InlineAsm::Constraint_v;
else if (ConstraintCode == "X")
return InlineAsm::Constraint_X;
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
/// Given a physical register constraint