forked from OSchip/llvm-project
[AMDGPU] Remove assertion on S1024 SGPR to VGPR spill
Summary: Replace an assertion that blocks S1024 SGPR to VGPR spill. The assertion pre-dates S1024 and is not wave size dependent. Reviewers: arsenm, sameerds, rampitec Reviewed By: arsenm Subscribers: qcolombet, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D80783
This commit is contained in:
Carl Ritson
parent
0892a96a05
commit
d04147789f
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@ -287,16 +287,19 @@ bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
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SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
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unsigned Size = FrameInfo.getObjectSize(FI);
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assert(Size >= 4 && Size <= 64 && "invalid sgpr spill size");
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assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
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unsigned NumLanes = Size / 4;
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int NumLanes = Size / 4;
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if (NumLanes > WaveSize)
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return false;
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assert(Size >= 4 && "invalid sgpr spill size");
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assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
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const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
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// Make sure to handle the case where a wide SGPR spill may span between two
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// VGPRs.
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for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
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for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
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Register LaneVGPR;
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unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
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@ -193,18 +193,236 @@ ret:
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ret void
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}
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; FIXME: x16 inlineasm seems broken
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; define amdgpu_kernel void @spill_sgpr_x16(i32 addrspace(1)* %out, i32 %in) #0 {
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; %wide.sgpr = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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; %cmp = icmp eq i32 %in, 0
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; br i1 %cmp, label %bb0, label %ret
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; ALL-LABEL: {{^}}spill_sgpr_x16:
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; bb0:
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; call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr) #0
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; br label %ret
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 8
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 9
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 10
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 11
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 12
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 13
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 14
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 15
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; VGPR: s_cbranch_scc1
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; ret:
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; ret void
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; }
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 8
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 9
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 10
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 11
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 12
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 13
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 14
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 15
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x16(i32 addrspace(1)* %out, i32 %in) #0 {
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%wide.sgpr = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; ALL-LABEL: {{^}}spill_sgpr_x32:
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 8
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 9
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 10
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 11
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 12
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 13
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 14
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 15
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 16
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 17
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 18
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 19
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 20
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 21
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 22
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 23
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 24
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 25
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 26
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 27
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 28
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 29
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 30
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 31
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 8
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 9
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 10
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 11
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 12
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 13
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 14
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 15
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 16
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 17
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 18
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 19
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 20
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 21
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 22
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 23
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 24
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 25
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 26
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 27
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 28
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 29
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 30
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 31
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x32(i32 addrspace(1)* %out, i32 %in) #0 {
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%wide.sgpr = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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attributes #0 = { nounwind }
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