forked from OSchip/llvm-project
Handle llvm.fma.* intrinsics. rdar://10914096
llvm-svn: 154439
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@ -769,8 +769,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FPOW, MVT::f64, Expand);
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setOperationAction(ISD::FPOW, MVT::f32, Expand);
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setOperationAction(ISD::FMA, MVT::f64, Expand);
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setOperationAction(ISD::FMA, MVT::f32, Expand);
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if (!Subtarget->hasVFP4()) {
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setOperationAction(ISD::FMA, MVT::f64, Expand);
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setOperationAction(ISD::FMA, MVT::f32, Expand);
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}
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// Various VFP goodness
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if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
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@ -4133,6 +4133,14 @@ def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
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v4f32, fmul_su, fsub_mlx>,
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Requires<[HasNEON2,FPContractions]>;
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// Match @llvm.fma.* intrinsics
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def : Pat<(fma (v2f32 DPR:$src1), (v2f32 DPR:$Vn), (v2f32 DPR:$Vm)),
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(VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasNEON, HasVFP4]>;
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def : Pat<(fma (v4f32 QPR:$src1), (v4f32 QPR:$Vn), (v4f32 QPR:$Vm)),
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(VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasNEON, HasVFP4]>;
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// Vector Subtract Operations.
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// VSUB : Vector Subtract (integer and floating-point)
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@ -1080,6 +1080,14 @@ def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
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(VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP4,DontUseNEONForFP,FPContractions]>;
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// Match @llvm.fma.* intrinsics
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def : Pat<(fma (f64 DPR:$Ddin), (f64 DPR:$Dn), (f64 DPR:$Dm)),
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(VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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def : Pat<(fma (f32 SPR:$Sdin), (f32 SPR:$Sn), (f32 SPR:$Sm)),
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(VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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def VFMSD : ADbI<0b11101, 0b10, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
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@ -0,0 +1,30 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mattr=+vfp4 | FileCheck %s
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define float @test_f32(float %a, float %b, float %c) nounwind readnone ssp {
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entry:
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; CHECK: test_f32
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; CHECK: vfma.f32
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%call = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone
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ret float %call
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}
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define double @test_f64(double %a, double %b, double %c) nounwind readnone ssp {
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entry:
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; CHECK: test_f64
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; CHECK: vfma.f64
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%call = tail call double @llvm.fma.f64(double %a, double %b, double %c) nounwind readnone
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ret double %call
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}
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define <2 x float> @test_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone ssp {
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entry:
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; CHECK: test_v2f32
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; CHECK: vfma.f32
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%0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
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ret <2 x float> %0
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}
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declare float @llvm.fma.f32(float, float, float) nounwind readnone
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declare double @llvm.fma.f64(double, double, double) nounwind readnone
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declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
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