GlobalISel: Remove explicit enumerator values from .def file.

They were all auto-incremented from 0 anyway, and I'm getting really annoying
conflicts and runtime failures when different people add more for GlobalISel
(and even when I'm refactoring my own patches).

NFC.

llvm-svn: 276204

llvm/include/llvm/Target/TargetOpcodes.def

@@ -27,22 +27,22 @@
 
 /// Every instruction defined here must also appear in Target.td.
 ///
-HANDLE_TARGET_OPCODE(PHI, 0)
-HANDLE_TARGET_OPCODE(INLINEASM, 1)
-HANDLE_TARGET_OPCODE(CFI_INSTRUCTION, 2)
-HANDLE_TARGET_OPCODE(EH_LABEL, 3)
-HANDLE_TARGET_OPCODE(GC_LABEL, 4)
+HANDLE_TARGET_OPCODE(PHI)
+HANDLE_TARGET_OPCODE(INLINEASM)
+HANDLE_TARGET_OPCODE(CFI_INSTRUCTION)
+HANDLE_TARGET_OPCODE(EH_LABEL)
+HANDLE_TARGET_OPCODE(GC_LABEL)
 
 /// KILL - This instruction is a noop that is used only to adjust the
 /// liveness of registers. This can be useful when dealing with
 /// sub-registers.
-HANDLE_TARGET_OPCODE(KILL, 5)
+HANDLE_TARGET_OPCODE(KILL)
 
 /// EXTRACT_SUBREG - This instruction takes two operands: a register
 /// that has subregisters, and a subregister index. It returns the
 /// extracted subregister value. This is commonly used to implement
 /// truncation operations on target architectures which support it.
-HANDLE_TARGET_OPCODE(EXTRACT_SUBREG, 6)
+HANDLE_TARGET_OPCODE(EXTRACT_SUBREG)
 
 /// INSERT_SUBREG - This instruction takes three operands: a register that
 /// has subregisters, a register providing an insert value, and a
@@ -50,16 +50,16 @@ HANDLE_TARGET_OPCODE(EXTRACT_SUBREG, 6)
 /// value of the second register inserted. The first register is often
 /// defined by an IMPLICIT_DEF, because it is commonly used to implement
 /// anyext operations on target architectures which support it.
-HANDLE_TARGET_OPCODE(INSERT_SUBREG, 7)
+HANDLE_TARGET_OPCODE(INSERT_SUBREG)
 
 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
-HANDLE_TARGET_OPCODE(IMPLICIT_DEF, 8)
+HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
 
 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
 /// the first operand is an immediate integer constant. This constant is
 /// often zero, because it is commonly used to assert that the instruction
 /// defining the register implicitly clears the high bits.
-HANDLE_TARGET_OPCODE(SUBREG_TO_REG, 9)
+HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
 
 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
 /// register-to-register copy into a specific register class. This is only
@@ -67,10 +67,10 @@ HANDLE_TARGET_OPCODE(SUBREG_TO_REG, 9)
 /// virtual registers have been created for all the instructions, and it's
 /// only needed in cases where the register classes implied by the
 /// instructions are insufficient. It is emitted as a COPY MachineInstr.
-HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS, 10)
+  HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS)
 
 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
-HANDLE_TARGET_OPCODE(DBG_VALUE, 11)
+HANDLE_TARGET_OPCODE(DBG_VALUE)
 
 /// REG_SEQUENCE - This variadic instruction is used to form a register that
 /// represents a consecutive sequence of sub-registers. It's used as a
@@ -83,55 +83,55 @@ HANDLE_TARGET_OPCODE(DBG_VALUE, 11)
 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
 /// After register coalescing references of v1024 should be replace with
 /// v1027:3, v1025 with v1027:4, etc.
-HANDLE_TARGET_OPCODE(REG_SEQUENCE, 12)
+  HANDLE_TARGET_OPCODE(REG_SEQUENCE)
 
 /// COPY - Target-independent register copy. This instruction can also be
 /// used to copy between subregisters of virtual registers.
-HANDLE_TARGET_OPCODE(COPY, 13)
+  HANDLE_TARGET_OPCODE(COPY)
 
 /// BUNDLE - This instruction represents an instruction bundle. Instructions
 /// which immediately follow a BUNDLE instruction which are marked with
 /// 'InsideBundle' flag are inside the bundle.
-HANDLE_TARGET_OPCODE(BUNDLE, 14)
+HANDLE_TARGET_OPCODE(BUNDLE)
 
 /// Lifetime markers.
-HANDLE_TARGET_OPCODE(LIFETIME_START, 15)
-HANDLE_TARGET_OPCODE(LIFETIME_END, 16)
+HANDLE_TARGET_OPCODE(LIFETIME_START)
+HANDLE_TARGET_OPCODE(LIFETIME_END)
 
 /// A Stackmap instruction captures the location of live variables at its
 /// position in the instruction stream. It is followed by a shadow of bytes
 /// that must lie within the function and not contain another stackmap.
-HANDLE_TARGET_OPCODE(STACKMAP, 17)
+HANDLE_TARGET_OPCODE(STACKMAP)
 
 /// Patchable call instruction - this instruction represents a call to a
 /// constant address, followed by a series of NOPs. It is intended to
 /// support optimizations for dynamic languages (such as javascript) that
 /// rewrite calls to runtimes with more efficient code sequences.
 /// This also implies a stack map.
-HANDLE_TARGET_OPCODE(PATCHPOINT, 18)
+HANDLE_TARGET_OPCODE(PATCHPOINT)
 
 /// This pseudo-instruction loads the stack guard value. Targets which need
 /// to prevent the stack guard value or address from being spilled to the
 /// stack should override TargetLowering::emitLoadStackGuardNode and
 /// additionally expand this pseudo after register allocation.
-HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD, 19)
+HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD)
 
 /// Call instruction with associated vm state for deoptimization and list
 /// of live pointers for relocation by the garbage collector.  It is
 /// intended to support garbage collection with fully precise relocating
 /// collectors and deoptimizations in either the callee or caller.
-HANDLE_TARGET_OPCODE(STATEPOINT, 20)
+HANDLE_TARGET_OPCODE(STATEPOINT)
 
 /// Instruction that records the offset of a local stack allocation passed to
 /// llvm.localescape. It has two arguments: the symbol for the label and the
 /// frame index of the local stack allocation.
-HANDLE_TARGET_OPCODE(LOCAL_ESCAPE, 21)
+HANDLE_TARGET_OPCODE(LOCAL_ESCAPE)
 
 /// Loading instruction that may page fault, bundled with associated
 /// information on how to handle such a page fault.  It is intended to support
 /// "zero cost" null checks in managed languages by allowing LLVM to fold
 /// comparisons into existing memory operations.
-HANDLE_TARGET_OPCODE(FAULTING_LOAD_OP, 22)
+HANDLE_TARGET_OPCODE(FAULTING_LOAD_OP)
 
 /// Wraps a machine instruction to add patchability constraints.  An
 /// instruction wrapped in PATCHABLE_OP has to either have a minimum
@@ -140,30 +140,30 @@ HANDLE_TARGET_OPCODE(FAULTING_LOAD_OP, 22)
 /// second operand is an immediate denoting the opcode of the original
 /// instruction.  The rest of the operands are the operands of the
 /// original instruction.
-HANDLE_TARGET_OPCODE(PATCHABLE_OP, 23)
+HANDLE_TARGET_OPCODE(PATCHABLE_OP)
 
 /// This is a marker instruction which gets translated into a nop sled, useful
 /// for inserting instrumentation instructions at runtime.
-HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER, 24)
+HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER)
 
 /// Wraps a return instruction and its operands to enable adding nop sleds
 /// either before or after the return. The nop sleds are useful for inserting
 /// instrumentation instructions at runtime.
-HANDLE_TARGET_OPCODE(PATCHABLE_RET, 25)
+HANDLE_TARGET_OPCODE(PATCHABLE_RET)
 
 /// The following generic opcodes are not supposed to appear after ISel.
 /// This is something we might want to relax, but for now, this is convenient
 /// to produce diagnostics.
 
 /// Generic ADD instruction. This is an integer add.
-HANDLE_TARGET_OPCODE(G_ADD, 26)
+HANDLE_TARGET_OPCODE(G_ADD)
 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
 
 /// Generic Bitwise-OR instruction.
-HANDLE_TARGET_OPCODE(G_OR, 27)
+HANDLE_TARGET_OPCODE(G_OR)
 
 /// Generic BRANCH instruction. This is an unconditional branch.
-HANDLE_TARGET_OPCODE(G_BR, 28)
+HANDLE_TARGET_OPCODE(G_BR)
 
 // TODO: Add more generic opcodes as we move along.
 

llvm/include/llvm/Target/TargetOpcodes.h

@@ -20,7 +20,7 @@ namespace llvm {
 ///
 namespace TargetOpcode {
 enum {
-#define HANDLE_TARGET_OPCODE(OPC, NUM) OPC = NUM,
+#define HANDLE_TARGET_OPCODE(OPC) OPC,
 #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) IDENT = OPC,
 #include "llvm/Target/TargetOpcodes.def"
 };

llvm/utils/TableGen/CodeGenTarget.cpp

@@ -301,7 +301,7 @@ GetInstByName(const char *Name,
 /// their enum value.
 void CodeGenTarget::ComputeInstrsByEnum() const {
   static const char *const FixedInstrs[] = {
-#define HANDLE_TARGET_OPCODE(OPC, NUM) #OPC,
+#define HANDLE_TARGET_OPCODE(OPC) #OPC,
 #include "llvm/Target/TargetOpcodes.def"
       nullptr};
   const auto &Insts = getInstructions();