forked from OSchip/llvm-project
[RISCV] Add lowering for vp.fptosi and vp.sitofp.
This as an alternative version of D120641. Starting from the code here https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi/-/raw/EPI/llvm/lib/Target/RISCV/RISCVISelLowering.cpp but with some modifications to how the interim types are calculated, and adding support for f16. Still need to add fptosi for mask vectors. Lots of masked isel patterns added so we can pass the mask through the type changes. Reviewed By: frasercrmck, arcbbb Differential Revision: https://reviews.llvm.org/D122512
This commit is contained in:
Craig Topper
parent
1db59dc8e2
commit
cfe533da05
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@ -490,13 +490,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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ISD::VP_SHL, ISD::VP_REDUCE_ADD, ISD::VP_REDUCE_AND,
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ISD::VP_REDUCE_OR, ISD::VP_REDUCE_XOR, ISD::VP_REDUCE_SMAX,
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ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
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ISD::VP_MERGE, ISD::VP_SELECT};
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ISD::VP_MERGE, ISD::VP_SELECT, ISD::VP_FPTOSI};
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static const unsigned FloatingPointVPOps[] = {
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ISD::VP_FADD, ISD::VP_FSUB, ISD::VP_FMUL,
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ISD::VP_FDIV, ISD::VP_FNEG, ISD::VP_FMA,
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ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD, ISD::VP_REDUCE_FMIN,
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ISD::VP_REDUCE_FMAX, ISD::VP_MERGE, ISD::VP_SELECT};
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ISD::VP_REDUCE_FMAX, ISD::VP_MERGE, ISD::VP_SELECT,
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ISD::VP_SITOFP};
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if (!Subtarget.is64Bit()) {
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// We must custom-lower certain vXi64 operations on RV32 due to the vector
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@ -846,6 +847,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::AND, VT, Custom);
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setOperationAction(ISD::OR, VT, Custom);
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setOperationAction(ISD::XOR, VT, Custom);
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setOperationAction(ISD::VP_FPTOSI, VT, Custom);
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continue;
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}
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@ -3692,6 +3695,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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return lowerVPOp(Op, DAG, RISCVISD::FNEG_VL);
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case ISD::VP_FMA:
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return lowerVPOp(Op, DAG, RISCVISD::FMA_VL);
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case ISD::VP_FPTOSI:
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return lowerVPFPIntConvOp(Op, DAG, RISCVISD::FP_TO_SINT_VL);
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case ISD::VP_SITOFP:
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return lowerVPFPIntConvOp(Op, DAG, RISCVISD::SINT_TO_FP_VL);
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}
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}
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@ -6126,6 +6133,124 @@ SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG,
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return convertFromScalableVector(VT, VPOp, DAG, Subtarget);
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}
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// Lower Floating-Point/Integer Type-Convert VP SDNodes
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SDValue RISCVTargetLowering::lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
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unsigned RISCVISDOpc) const {
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SDLoc DL(Op);
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SDValue Src = Op.getOperand(0);
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SDValue Mask = Op.getOperand(1);
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SDValue VL = Op.getOperand(2);
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MVT DstVT = Op.getSimpleValueType();
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MVT SrcVT = Src.getSimpleValueType();
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if (DstVT.isFixedLengthVector()) {
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DstVT = getContainerForFixedLengthVector(DstVT);
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SrcVT = getContainerForFixedLengthVector(SrcVT);
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Src = convertToScalableVector(SrcVT, Src, DAG, Subtarget);
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MVT MaskVT = MVT::getVectorVT(MVT::i1, DstVT.getVectorElementCount());
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Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
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}
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unsigned RISCVISDExtOpc = (RISCVISDOpc == RISCVISD::SINT_TO_FP_VL ||
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RISCVISDOpc == RISCVISD::FP_TO_SINT_VL)
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? RISCVISD::VSEXT_VL
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: RISCVISD::VZEXT_VL;
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unsigned DstEltSize = DstVT.getScalarSizeInBits();
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unsigned SrcEltSize = SrcVT.getScalarSizeInBits();
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SDValue Result;
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if (DstEltSize >= SrcEltSize) { // Single-width and widening conversion.
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if (SrcVT.isInteger()) {
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assert(DstVT.isFloatingPoint() && "Wrong input/output vector types");
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// Do we need to do any pre-widening before converting?
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if (SrcEltSize == 1) {
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MVT IntVT = DstVT.changeVectorElementTypeToInteger();
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MVT XLenVT = Subtarget.getXLenVT();
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SDValue Zero = DAG.getConstant(0, DL, XLenVT);
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SDValue ZeroSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT,
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DAG.getUNDEF(IntVT), Zero, VL);
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SDValue One = DAG.getConstant(
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RISCVISDExtOpc == RISCVISD::VZEXT_VL ? 1 : -1, DL, XLenVT);
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SDValue OneSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT,
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DAG.getUNDEF(IntVT), One, VL);
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Src = DAG.getNode(RISCVISD::VSELECT_VL, DL, IntVT, Src, OneSplat,
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ZeroSplat, VL);
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} else if (DstEltSize > (2 * SrcEltSize)) {
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// Widen before converting.
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MVT IntVT = MVT::getVectorVT(MVT::getIntegerVT(DstEltSize / 2),
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DstVT.getVectorElementCount());
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Src = DAG.getNode(RISCVISDExtOpc, DL, IntVT, {Src, Mask, VL});
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}
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Result = DAG.getNode(RISCVISDOpc, DL, DstVT, {Src, Mask, VL});
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} else {
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assert(SrcVT.isFloatingPoint() && DstVT.isInteger() &&
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"Wrong input/output vector types");
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// Convert f16 to f32 then convert f32 to i64.
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if (DstEltSize > (2 * SrcEltSize)) {
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assert(SrcVT.getVectorElementType() == MVT::f16 && "Unexpected type!");
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MVT InterimFVT =
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MVT::getVectorVT(MVT::f32, DstVT.getVectorElementCount());
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Src = DAG.getNode(RISCVISD::FP_EXTEND_VL, DL, InterimFVT,
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{Src, Mask, VL});
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}
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Result = DAG.getNode(RISCVISDOpc, DL, DstVT, {Src, Mask, VL});
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}
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} else { // Narrowing + Conversion
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if (SrcVT.isInteger()) {
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assert(DstVT.isFloatingPoint() && "Wrong input/output vector types");
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// First do a narrowing convert to an FP type half the size, then round
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// the FP type to a small FP type if needed.
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MVT InterimFVT = DstVT;
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if (SrcEltSize > (2 * DstEltSize)) {
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assert(SrcEltSize == (4 * DstEltSize) && "Unexpected types!");
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assert(DstVT.getVectorElementType() == MVT::f16 && "Unexpected type!");
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InterimFVT = MVT::getVectorVT(MVT::f32, DstVT.getVectorElementCount());
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}
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Result = DAG.getNode(RISCVISDOpc, DL, InterimFVT, {Src, Mask, VL});
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if (InterimFVT != DstVT) {
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Src = Result;
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Result = DAG.getNode(RISCVISD::FP_ROUND_VL, DL, DstVT, {Src, Mask, VL});
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}
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} else {
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assert(SrcVT.isFloatingPoint() && DstVT.isInteger() &&
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"Wrong input/output vector types");
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// First do a narrowing conversion to an integer half the size, then
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// truncate if needed.
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// TODO: Handle mask vectors
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assert(DstVT.getVectorElementType() != MVT::i1 &&
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"Don't know how to handle masks yet!");
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MVT InterimIVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize / 2),
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DstVT.getVectorElementCount());
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Result = DAG.getNode(RISCVISDOpc, DL, InterimIVT, {Src, Mask, VL});
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while (InterimIVT != DstVT) {
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SrcEltSize /= 2;
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Src = Result;
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InterimIVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize / 2),
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DstVT.getVectorElementCount());
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Result = DAG.getNode(RISCVISD::TRUNCATE_VECTOR_VL, DL, InterimIVT,
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{Src, Mask, VL});
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}
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}
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}
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MVT VT = Op.getSimpleValueType();
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if (!VT.isFixedLengthVector())
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return Result;
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return convertFromScalableVector(VT, Result, DAG, Subtarget);
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}
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SDValue RISCVTargetLowering::lowerLogicVPOp(SDValue Op, SelectionDAG &DAG,
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unsigned MaskOpc,
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unsigned VecOpc) const {
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@ -647,6 +647,8 @@ private:
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SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const;
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SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
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unsigned VecOpc) const;
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SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
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unsigned RISCVISDOpc) const;
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SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
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unsigned ExtendOpc) const;
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SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
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@ -553,6 +553,12 @@ multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix,
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true_mask, VLOpFrag)),
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(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
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fti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
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def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2),
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(fti.Mask V0), VLOpFrag)),
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(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX#"_MASK")
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(vti.Vector (IMPLICIT_DEF)),
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fti.RegClass:$rs2,
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(fti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
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}
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}
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@ -564,6 +570,12 @@ multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
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fvti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>;
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def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Mask V0),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
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(ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
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(fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>;
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}
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}
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@ -575,6 +587,12 @@ multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
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ivti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
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(ivti.Mask V0),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
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(fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
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(ivti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
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}
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}
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@ -587,6 +605,12 @@ multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Mask V0),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
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(iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
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(fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
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}
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}
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@ -599,6 +623,12 @@ multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
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ivti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>;
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def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
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(ivti.Mask V0),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
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(fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
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(ivti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>;
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}
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}
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@ -611,6 +641,12 @@ multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#vti.LMul.MX)
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fwti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
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def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
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(fwti.Mask V0),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK")
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(vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
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(fwti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
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}
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}
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@ -623,6 +659,12 @@ multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
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iwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
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(iwti.Mask V0),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
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(fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1,
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(iwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
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}
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}
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@ -808,6 +850,12 @@ foreach vtiTowti = AllWidenableIntVectors in {
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VLOpFrag)),
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(!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX)
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wti.RegClass:$rs1, X0, GPR:$vl, vti.Log2SEW)>;
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def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1),
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(vti.Mask V0),
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VLOpFrag)),
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(!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX#"_MASK")
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(vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, X0,
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(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
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def : Pat<(vti.Vector
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(riscv_trunc_vector_vl
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@ -1504,6 +1552,12 @@ foreach fvti = AllFloatVectors in {
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VLOpFrag)),
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(!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Mask V0),
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VLOpFrag)),
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(!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_MASK")
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(fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
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(fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
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}
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// 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions
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@ -1519,6 +1573,12 @@ foreach fvti = AllFloatVectors in {
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VLOpFrag)),
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(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
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fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1),
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(fwti.Mask V0),
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VLOpFrag)),
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(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK")
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(fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
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(fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
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def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1),
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(fwti.Mask true_mask),
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@ -0,0 +1,300 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh \
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; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh \
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; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s
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declare <4 x i8> @llvm.vp.fptosi.v4i8.v4f16(<4 x half>, <4 x i1>, i32)
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define <4 x i8> @vfptosi_v4i8_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vfptosi_v4i8_v4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
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; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
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ret <4 x i8> %v
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}
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define <4 x i8> @vfptosi_v4i8_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
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||||
; CHECK-LABEL: vfptosi_v4i8_v4f16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i8> %v
|
||||
}
|
||||
|
||||
declare <4 x i16> @llvm.vp.fptosi.v4i16.v4f16(<4 x half>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i16> @vfptosi_v4i16_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i16_v4f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i16> %v
|
||||
}
|
||||
|
||||
define <4 x i16> @vfptosi_v4i16_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i16_v4f16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i16> %v
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.vp.fptosi.v4i32.v4f16(<4 x half>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i32> @vfptosi_v4i32_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i32_v4f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i32> %v
|
||||
}
|
||||
|
||||
define <4 x i32> @vfptosi_v4i32_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i32_v4f16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i32> %v
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.vp.fptosi.v4i64.v4f16(<4 x half>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i64> @vfptosi_v4i64_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i64_v4f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.f.v v10, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
define <4 x i64> @vfptosi_v4i64_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i64_v4f16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.f.v v10, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
declare <4 x i8> @llvm.vp.fptosi.v4i8.v4f32(<4 x float>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i8> @vfptosi_v4i8_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i8_v4f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v9, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i8> %v
|
||||
}
|
||||
|
||||
define <4 x i8> @vfptosi_v4i8_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i8_v4f32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i8> %v
|
||||
}
|
||||
|
||||
declare <4 x i16> @llvm.vp.fptosi.v4i16.v4f32(<4 x float>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i16> @vfptosi_v4i16_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i16_v4f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i16> %v
|
||||
}
|
||||
|
||||
define <4 x i16> @vfptosi_v4i16_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i16_v4f32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i16> %v
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.vp.fptosi.v4i32.v4f32(<4 x float>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i32> @vfptosi_v4i32_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i32_v4f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i32> %v
|
||||
}
|
||||
|
||||
define <4 x i32> @vfptosi_v4i32_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i32_v4f32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i32> %v
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.vp.fptosi.v4i64.v4f32(<4 x float>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i64> @vfptosi_v4i64_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i64_v4f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8, v0.t
|
||||
; CHECK-NEXT: vmv2r.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
define <4 x i64> @vfptosi_v4i64_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i64_v4f32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
|
||||
; CHECK-NEXT: vmv2r.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
declare <4 x i8> @llvm.vp.fptosi.v4i8.v4f64(<4 x double>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i8> @vfptosi_v4i8_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i8_v4f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v10, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i8> %v
|
||||
}
|
||||
|
||||
define <4 x i8> @vfptosi_v4i8_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i8_v4f64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v10
|
||||
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i8> %v
|
||||
}
|
||||
|
||||
declare <4 x i16> @llvm.vp.fptosi.v4i16.v4f64(<4 x double>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i16> @vfptosi_v4i16_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i16_v4f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i16> %v
|
||||
}
|
||||
|
||||
define <4 x i16> @vfptosi_v4i16_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i16_v4f64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i16> %v
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.vp.fptosi.v4i32.v4f64(<4 x double>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i32> @vfptosi_v4i32_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i32_v4f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vmv.v.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i32> %v
|
||||
}
|
||||
|
||||
define <4 x i32> @vfptosi_v4i32_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i32_v4f64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
|
||||
; CHECK-NEXT: vmv.v.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i32> %v
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.vp.fptosi.v4i64.v4f64(<4 x double>, <4 x i1>, i32)
|
||||
|
||||
define <4 x i64> @vfptosi_v4i64_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i64_v4f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
define <4 x i64> @vfptosi_v4i64_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_v4i64_v4f64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh \
|
||||
; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh \
|
||||
; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s
|
||||
|
||||
declare <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1>, <4 x i1>, i32)
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v9, 0
|
||||
; CHECK-NEXT: vmerge.vim v9, v9, -1, v0
|
||||
; CHECK-NEXT: vmv1r.v v0, v8
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i1_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v8, 0
|
||||
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1>, <4 x i1>, i32)
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v9, 0
|
||||
; CHECK-NEXT: vmerge.vim v9, v9, -1, v0
|
||||
; CHECK-NEXT: vmv1r.v v0, v8
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i1_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v8, 0
|
||||
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1>, <4 x i1>, i32)
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v10, 0
|
||||
; CHECK-NEXT: vmerge.vim v10, v10, -1, v0
|
||||
; CHECK-NEXT: vmv1r.v v0, v8
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i1_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v8, 0
|
||||
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
|
@ -0,0 +1,289 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh \
|
||||
; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh \
|
||||
; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s
|
||||
|
||||
declare <4 x half> @llvm.vp.sitofp.v4f16.v4i8(<4 x i8>, <4 x i1>, i32)
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i8_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
declare <4 x half> @llvm.vp.sitofp.v4f16.v4i16(<4 x i16>, <4 x i1>, i32)
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
declare <4 x half> @llvm.vp.sitofp.v4f16.v4i32(<4 x i32>, <4 x i1>, i32)
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
declare <4 x half> @llvm.vp.sitofp.v4f16.v4i64(<4 x i64>, <4 x i1>, i32)
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
define <4 x half> @vsitofp_v4f16_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f16_v4i64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v10, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.f.w v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.vp.sitofp.v4f32.v4i8(<4 x i8>, <4 x i1>, i32)
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vsext.vf2 v9, v8, v0.t
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i8_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vsext.vf2 v9, v8
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.vp.sitofp.v4f32.v4i16(<4 x i16>, <4 x i1>, i32)
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32>, <4 x i1>, i32)
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.vp.sitofp.v4f32.v4i64(<4 x i64>, <4 x i1>, i32)
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vmv.v.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
define <4 x float> @vsitofp_v4f32_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f32_v4i64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v10, v8
|
||||
; CHECK-NEXT: vmv.v.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.vp.sitofp.v4f64.v4i8(<4 x i8>, <4 x i1>, i32)
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vsext.vf4 v10, v8, v0.t
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i8_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vsext.vf4 v10, v8
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.vp.sitofp.v4f64.v4i16(<4 x i16>, <4 x i1>, i32)
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vsext.vf2 v10, v8, v0.t
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vsext.vf2 v10, v8
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.vp.sitofp.v4f64.v4i32(<4 x i32>, <4 x i1>, i32)
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v10, v8, v0.t
|
||||
; CHECK-NEXT: vmv2r.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v10, v8
|
||||
; CHECK-NEXT: vmv2r.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.vp.sitofp.v4f64.v4i64(<4 x i64>, <4 x i1>, i32)
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
define <4 x double> @vsitofp_v4f64_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_v4f64_v4i64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
|
@ -0,0 +1,297 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
|
||||
|
||||
declare <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i8_nxv2f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i8> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i8_nxv2f16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i16_nxv2f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i16> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i16_nxv2f16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i32_nxv2f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i32_nxv2f16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i64_nxv2f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.f.v v10, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i64_nxv2f16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.f.v v10, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f32(<vscale x 2 x float>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i8_nxv2f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v9, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i8> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i8_nxv2f32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f32(<vscale x 2 x float>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i16_nxv2f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i16> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i16_nxv2f32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f32(<vscale x 2 x float>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i32_nxv2f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i32_nxv2f32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f32(<vscale x 2 x float>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i64_nxv2f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8, v0.t
|
||||
; CHECK-NEXT: vmv2r.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i64_nxv2f32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
|
||||
; CHECK-NEXT: vmv2r.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i8_nxv2f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v10, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i8> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i8_nxv2f64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v10
|
||||
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i16_nxv2f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i16> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i16_nxv2f64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vncvt.x.x.w v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i32_nxv2f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vmv.v.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i32_nxv2f64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
|
||||
; CHECK-NEXT: vmv.v.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i64_nxv2f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vfptosi_nxv2i64_nxv2f64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
|
||||
|
||||
declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v9, 0
|
||||
; CHECK-NEXT: vmerge.vim v9, v9, -1, v0
|
||||
; CHECK-NEXT: vmv1r.v v0, v8
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i1_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v8, 0
|
||||
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v9, 0
|
||||
; CHECK-NEXT: vmerge.vim v9, v9, -1, v0
|
||||
; CHECK-NEXT: vmv1r.v v0, v8
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i1_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v8, 0
|
||||
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v10, 0
|
||||
; CHECK-NEXT: vmerge.vim v10, v10, -1, v0
|
||||
; CHECK-NEXT: vmv1r.v v0, v8
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i1_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vmv.v.i v8, 0
|
||||
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
|
||||
|
||||
declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i8_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v10, v8
|
||||
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.f.w v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vsext.vf2 v9, v8, v0.t
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i8_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vsext.vf2 v9, v8
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v9, v8, v0.t
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v9, v8
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v10, v8, v0.t
|
||||
; CHECK-NEXT: vmv.v.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfncvt.f.x.w v10, v8
|
||||
; CHECK-NEXT: vmv.v.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vsext.vf4 v10, v8, v0.t
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i8_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vsext.vf4 v10, v8
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vsext.vf2 v10, v8, v0.t
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i16_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vsext.vf2 v10, v8
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v10, v8, v0.t
|
||||
; CHECK-NEXT: vmv2r.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i32_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vfwcvt.f.x.v v10, v8
|
||||
; CHECK-NEXT: vmv2r.v v8, v10
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32)
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i64:
|
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; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
|
||||
; CHECK-LABEL: vsitofp_nxv2f64_nxv2i64_unmasked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
|
||||
ret <vscale x 2 x double> %v
|
||||
}
|
||||
Loading…
Reference in New Issue