From cfd4c333448bf9d691fad2de20443abc73d4fecd Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail@cn.ibm.com>
Date: Thu, 11 Jul 2019 09:43:03 +0000
Subject: [PATCH] [NFC][PowerPC] Added test to track current behaviour of
 TailDup

llvm-svn: 365746
---
 .../PowerPC/redundant-copy-after-tail-dup.ll  | 73 +++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll

diff --git a/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll b/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
new file mode 100644
index 000000000000..6aaf169dabee
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names -verify-machineinstrs -O3 < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-P9
+
+%class.A = type <{ %"class.D", %"class.D", i32, i32, i32, %"class.B", %"class.C", %"class.C", %"class.C", %"class.C", %"class.D", [2 x i8], %"class.E", %"class.F", %"class.G", %"class.G", %"class.H", i32, [4 x i8] }>
+%"class.B" = type { [441 x i32] }
+%"class.C" = type { [442 x i16] }
+%"class.D" = type { [441 x i16] }
+%"class.E" = type { [4 x i32] }
+%"class.F" = type { [8 x i32] }
+%"class.G" = type { [2 x i32] }
+%"class.H" = type { %"struct.A" }
+%"struct.A" = type { %"struct.B" }
+%"struct.B" = type { i32*, i32*, i32* }
+
+define dso_local i1 @t(%class.A* %this, i32 %color, i32 %vertex) local_unnamed_addr {
+; CHECK-P9-LABEL: t:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    li r5, 1
+; CHECK-P9-NEXT:    bc 12, 4*cr5+lt, .LBB0_4
+; CHECK-P9-NEXT:  # %bb.1: # %land.lhs.true
+; CHECK-P9-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
+; CHECK-P9-NEXT:  .LBB0_2: # %for.inc
+; CHECK-P9-NEXT:    lhz r3, 5308(r3)
+; CHECK-P9-NEXT:    cmplwi r3, 2
+; CHECK-P9-NEXT:    bge- cr0, .LBB0_6
+; CHECK-P9-NEXT:  # %bb.3: # %land.lhs.true.1
+; CHECK-P9-NEXT:    li r5, 0
+; CHECK-P9-NEXT:    mr r3, r5
+; CHECK-P9-NEXT:    blr
+; CHECK-P9-NEXT:  .LBB0_4: # %lor.lhs.false
+; CHECK-P9-NEXT:    cmplwi cr0, r4, 0
+; CHECK-P9-NEXT:    bne cr0, .LBB0_2
+; CHECK-P9-NEXT:  .LBB0_5: # %cleanup16
+; CHECK-P9-NEXT:    mr r3, r5
+; CHECK-P9-NEXT:    blr
+; CHECK-P9-NEXT:  .LBB0_6: # %lor.lhs.false.1
+entry:
+  br i1 undef, label %land.lhs.true, label %lor.lhs.false
+
+land.lhs.true:                                    ; preds = %entry
+  br i1 undef, label %cleanup16, label %for.inc
+
+lor.lhs.false:                                    ; preds = %entry
+  %cmp11 = icmp ne i16 0, 2
+  %cmp13 = icmp eq i32 0, %color
+  %or.cond = and i1 %cmp13, %cmp11
+  br i1 %or.cond, label %cleanup16, label %for.inc
+
+for.inc:                                          ; preds = %lor.lhs.false, %land.lhs.true
+  %arrayidx.i31.1 = getelementptr inbounds %class.A, %class.A* %this, i64 0, i32 8, i32 0, i64 undef
+  %0 = load i16, i16* %arrayidx.i31.1, align 2
+  %cmp8.1 = icmp ult i16 %0, 2
+  br i1 %cmp8.1, label %land.lhs.true.1, label %lor.lhs.false.1
+
+cleanup16:                                        ; preds = %for.inc.2, %lor.lhs.false.2, %lor.lhs.false, %land.lhs.true
+  %1 = phi i1 [ true, %land.lhs.true ], [ true, %lor.lhs.false ], [ true, %lor.lhs.false.2 ], [ false, %for.inc.2 ]
+  ret i1 %1
+
+lor.lhs.false.1:                                  ; preds = %for.inc
+  unreachable
+
+land.lhs.true.1:                                  ; preds = %for.inc
+  br label %lor.lhs.false.2
+
+lor.lhs.false.2:                                  ; preds = %land.lhs.true.1
+  br i1 false, label %cleanup16, label %for.inc.2
+
+for.inc.2:                                        ; preds = %lor.lhs.false.2
+  br label %cleanup16
+}
+