forked from OSchip/llvm-project
AMDGPU: Support shrinking add with FI in SIFoldOperands
Avoids test regression in a future patch llvm-svn: 359898
This commit is contained in:
Matt Arsenault
parent
e28ab93546
commit
cfd0ca38b0
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@ -216,53 +216,55 @@ static bool updateOperand(FoldCandidate &Fold,
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break;
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}
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}
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}
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if (Fold.needsShrink()) {
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MachineBasicBlock *MBB = MI->getParent();
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auto Liveness = MBB->computeRegisterLiveness(&TRI, AMDGPU::VCC, MI);
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if (Liveness != MachineBasicBlock::LQR_Dead)
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return false;
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if ((Fold.isImm() || Fold.isFI()) && Fold.needsShrink()) {
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MachineBasicBlock *MBB = MI->getParent();
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auto Liveness = MBB->computeRegisterLiveness(&TRI, AMDGPU::VCC, MI);
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if (Liveness != MachineBasicBlock::LQR_Dead)
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return false;
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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int Op32 = Fold.getShrinkOpcode();
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MachineOperand &Dst0 = MI->getOperand(0);
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MachineOperand &Dst1 = MI->getOperand(1);
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assert(Dst0.isDef() && Dst1.isDef());
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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int Op32 = Fold.getShrinkOpcode();
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MachineOperand &Dst0 = MI->getOperand(0);
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MachineOperand &Dst1 = MI->getOperand(1);
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assert(Dst0.isDef() && Dst1.isDef());
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bool HaveNonDbgCarryUse = !MRI.use_nodbg_empty(Dst1.getReg());
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bool HaveNonDbgCarryUse = !MRI.use_nodbg_empty(Dst1.getReg());
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const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
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unsigned NewReg0 = MRI.createVirtualRegister(Dst0RC);
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const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
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unsigned NewReg0 = MRI.createVirtualRegister(Dst0RC);
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MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32);
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MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32);
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if (HaveNonDbgCarryUse) {
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BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg())
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.addReg(AMDGPU::VCC, RegState::Kill);
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}
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// Keep the old instruction around to avoid breaking iterators, but
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// replace it with a dummy instruction to remove uses.
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//
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// FIXME: We should not invert how this pass looks at operands to avoid
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// this. Should track set of foldable movs instead of looking for uses
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// when looking at a use.
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Dst0.setReg(NewReg0);
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for (unsigned I = MI->getNumOperands() - 1; I > 0; --I)
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MI->RemoveOperand(I);
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MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF));
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if (Fold.isCommuted())
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TII.commuteInstruction(*Inst32, false);
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return true;
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if (HaveNonDbgCarryUse) {
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BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg())
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.addReg(AMDGPU::VCC, RegState::Kill);
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}
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Old.ChangeToImmediate(Fold.ImmToFold);
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// Keep the old instruction around to avoid breaking iterators, but
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// replace it with a dummy instruction to remove uses.
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//
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// FIXME: We should not invert how this pass looks at operands to avoid
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// this. Should track set of foldable movs instead of looking for uses
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// when looking at a use.
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Dst0.setReg(NewReg0);
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for (unsigned I = MI->getNumOperands() - 1; I > 0; --I)
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MI->RemoveOperand(I);
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MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF));
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if (Fold.isCommuted())
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TII.commuteInstruction(*Inst32, false);
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return true;
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}
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assert(!Fold.needsShrink() && "not handled");
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if (Fold.isImm()) {
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Old.ChangeToImmediate(Fold.ImmToFold);
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return true;
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}
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if (Fold.isFI()) {
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Old.ChangeToFrameIndex(Fold.FrameIndexToFold);
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return true;
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@ -363,7 +365,7 @@ static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
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if ((Opc == AMDGPU::V_ADD_I32_e64 ||
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Opc == AMDGPU::V_SUB_I32_e64 ||
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Opc == AMDGPU::V_SUBREV_I32_e64) && // FIXME
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OpToFold->isImm()) {
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(OpToFold->isImm() || OpToFold->isFI())) {
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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// Verify the other operand is a VGPR, otherwise we would violate the
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@ -16,8 +16,8 @@ body: |
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; GCN: liveins: $vgpr0
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[COPY]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[V_MOV_B32_e32_]], [[COPY]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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%0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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%1:vgpr_32 = COPY $vgpr0
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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@ -40,8 +40,8 @@ body: |
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[COPY]], [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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@ -64,7 +64,7 @@ body: |
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; GCN: liveins: $sgpr0
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[COPY]], 0, implicit $exec
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
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%0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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%1:sreg_32_xm0 = COPY $sgpr0
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@ -88,7 +88,7 @@ body: |
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[COPY]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
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%0:sreg_32_xm0 = COPY $sgpr0
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%1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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@ -112,8 +112,8 @@ body: |
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; GCN: liveins: $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[COPY]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[COPY]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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%0:sreg_32_xm0 = S_MOV_B32 %stack.0
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%1:vgpr_32 = COPY $vgpr0
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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@ -136,8 +136,8 @@ body: |
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[COPY]], [[S_MOV_B32_]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[COPY]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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%0:vgpr_32 = COPY $vgpr0
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%1:sreg_32_xm0 = S_MOV_B32 %stack.0
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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@ -157,8 +157,8 @@ body: |
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; GCN-LABEL: name: shrink_vgpr_imm_fi_vgpr_v_add_i32_e64_no_carry_out_use
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], 16, 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 16, [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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%0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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%1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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@ -199,8 +199,7 @@ body: |
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; GCN-LABEL: name: shrink_vgpr_k_fi_vgpr_v_add_i32_e64_no_carry_out_use
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit-def $vcc, implicit $exec
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 1234, [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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%0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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%1:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
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