Do not use register as base ptr of pre- and post- inc/dec load / store nodes.

llvm-svn: 71098

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -4536,7 +4536,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
 
   // Check #1.  Preinc'ing a frame index would require copying the stack pointer
   // (plus the implicit offset) to a register to preinc anyway.
-  if (isa<FrameIndexSDNode>(BasePtr))
+  if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
     return false;
 
   // Check #2.
@@ -4663,6 +4663,9 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
       //    nor a successor of N. Otherwise, if Op is folded that would
       //    create a cycle.
 
+      if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
+        continue;
+
       // Check for #1.
       bool TryNext = false;
       for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),

llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll

@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6
+; PR4166
+
+	%"byte[]" = type { i32, i8* }
+	%tango.time.Time.Time = type { i64 }
+
+define fastcc void @t() {
+entry:
+	%tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null)		; <i1> [#uses=0]
+	ret void
+}