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Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not 

just pretend to be.

llvm-svn: 119602
This commit is contained in:
Jim Grosbach 2010-11-18 01:15:56 +00:00
parent d127e7174b
commit cfb66204b7
2 changed files with 26 additions and 43 deletions
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27
llvm/lib/Target/ARM/ARMInstrFormats.td
View File

@ -244,6 +244,14 @@ class PseudoInst<dag oops, dag iops, InstrItinClass itin,
let Pattern = pattern;
}
// PseudoInst that's ARM-mode only.
class ARMPseudoInst<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: PseudoInst<oops, iops, itin, asm, pattern> {
list<Predicate> Predicates = [IsARM];
}
// Almost all ARM instructions are predicable.
class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, InstrItinClass itin,
@ -519,25 +527,6 @@ class AI3ld<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{7-4} = op;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AXI3ld<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern> {
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = op;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
// loads
class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>

42
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -1118,37 +1118,31 @@ def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
}
// Address computation and loads and stores in PIC mode.
// FIXME: These PIC insn patterns are pseudos, but derive from the normal insn
// classes (AXI1, et.al.) and so have encoding information and such,
// which is suboptimal. Once the rest of the code emitter (including
// JIT) is MC-ized we should look at refactoring these into true
// pseudos. As is, the encoding information ends up being ignored,
// as these instructions are lowered to individual MC-insts.
let isNotDuplicable = 1 in {
def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
Pseudo, IIC_iALUr, "",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
IIC_iALUr, "",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
let AddedComplexity = 10 in {
def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_r, "",
[(set GPR:$dst, (load addrmodepc:$addr))]>;
def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
IIC_iLoad_r, "",
[(set GPR:$dst, (load addrmodepc:$addr))]>;
def PICLDRH : AXI3ld<0b1011, (outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
IIC_iLoad_bh_r, "",
[(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
def PICLDRB : AXI2ldb<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
IIC_iLoad_bh_r, "",
[(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
def PICLDRSH : AXI3ld<0b1111, (outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
IIC_iLoad_bh_r, "",
[(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
def PICLDRSB : AXI3ld<0b1101, (outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
IIC_iLoad_bh_r, "",
[(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
}
let AddedComplexity = 10 in {
def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),