forked from OSchip/llvm-project
[RISCV] Add -mtune support
- The goal of this patch is improve option compatible with RISCV-V GCC,
-mcpu support on GCC side will sent patch in next few days.
- -mtune only affect the pipeline model and non-arch/extension related
target feature, e.g. instruction fusion; in td file it called
TuneFeatures, which is introduced by X86 back-end[1].
- -mtune accept all valid option for -mcpu and extra alias processor
option, e.g. `generic`, `rocket` and `sifive-7-series`, the purpose is
option compatible with RISCV-V GCC.
- Processor alias for -mtune will resolve according the current target arch,
rv32 or rv64, e.g. `rocket` will resolve to `rocket-rv32` or `rocket-rv64`.
- Interaction between -mcpu and -mtune:
* -mtune has higher priority than -mcpu for pipeline model and
TuneFeatures.
[1] https://reviews.llvm.org/D85165
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D89025
This commit is contained in:
Kito Cheng
parent
19ae9b6e21
commit
cfa7094e49
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@ -2768,7 +2768,7 @@ def module_file_info : Flag<["-"], "module-file-info">, Flags<[DriverOption,CC1O
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HelpText<"Provide information about a particular module file">;
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def mthumb : Flag<["-"], "mthumb">, Group<m_Group>;
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def mtune_EQ : Joined<["-"], "mtune=">, Group<m_Group>,
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HelpText<"Only supported on X86. Otherwise accepted for compatibility with GCC.">;
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HelpText<"Only supported on X86 and RISC-V. Otherwise accepted for compatibility with GCC.">;
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def multi__module : Flag<["-"], "multi_module">;
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def multiply__defined__unused : Separate<["-"], "multiply_defined_unused">;
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def multiply__defined : Separate<["-"], "multiply_defined">;
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@ -178,6 +178,17 @@ void RISCV32TargetInfo::fillValidCPUList(
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llvm::RISCV::fillValidCPUArchList(Values, false);
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}
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bool RISCV32TargetInfo::isValidTuneCPUName(StringRef Name) const {
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return llvm::RISCV::checkTuneCPUKind(
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llvm::RISCV::parseTuneCPUKind(Name, false),
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/*Is64Bit=*/false);
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}
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void RISCV32TargetInfo::fillValidTuneCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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llvm::RISCV::fillValidTuneCPUArchList(Values, false);
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}
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bool RISCV64TargetInfo::isValidCPUName(StringRef Name) const {
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return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name),
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/*Is64Bit=*/true);
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@ -187,3 +198,14 @@ void RISCV64TargetInfo::fillValidCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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llvm::RISCV::fillValidCPUArchList(Values, true);
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}
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bool RISCV64TargetInfo::isValidTuneCPUName(StringRef Name) const {
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return llvm::RISCV::checkTuneCPUKind(
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llvm::RISCV::parseTuneCPUKind(Name, true),
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/*Is64Bit=*/true);
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}
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void RISCV64TargetInfo::fillValidTuneCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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llvm::RISCV::fillValidTuneCPUArchList(Values, true);
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}
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@ -106,6 +106,8 @@ public:
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bool isValidCPUName(StringRef Name) const override;
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool isValidTuneCPUName(StringRef Name) const override;
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void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
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void setMaxAtomicWidth() override {
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MaxAtomicPromoteWidth = 128;
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@ -133,6 +135,8 @@ public:
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bool isValidCPUName(StringRef Name) const override;
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool isValidTuneCPUName(StringRef Name) const override;
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void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
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void setMaxAtomicWidth() override {
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MaxAtomicPromoteWidth = 128;
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@ -2012,6 +2012,20 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
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CmdArgs.push_back(ABIName.data());
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SetRISCVSmallDataLimit(getToolChain(), Args, CmdArgs);
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std::string TuneCPU;
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if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_mtune_EQ)) {
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StringRef Name = A->getValue();
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Name = llvm::RISCV::resolveTuneCPUAlias(Name, Triple.isArch64Bit());
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TuneCPU = std::string(Name);
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}
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if (!TuneCPU.empty()) {
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CmdArgs.push_back("-tune-cpu");
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CmdArgs.push_back(Args.MakeArgString(TuneCPU));
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}
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}
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void Clang::AddSparcTargetArgs(const ArgList &Args,
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@ -14,6 +14,37 @@
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// MCPU-SIFIVE7-64: "-nostdsysteminc" "-target-cpu" "sifive-7-rv64"
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// MCPU-SIFIVE7-64: "-target-feature" "+64bit"
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// RUN: %clang -target riscv32 -### -c %s 2>&1 -mtune=rocket-rv32 | FileCheck -check-prefix=MTUNE-ROCKET32 %s
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// MTUNE-ROCKET32: "-tune-cpu" "rocket-rv32"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck -check-prefix=MTUNE-ROCKET64 %s
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// MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64"
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// RUN: %clang -target riscv32 -### -c %s 2>&1 -mtune=sifive-7-rv32 | FileCheck -check-prefix=MTUNE-SIFIVE7-32 %s
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// MTUNE-SIFIVE7-32: "-tune-cpu" "sifive-7-rv32"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-rv64 | FileCheck -check-prefix=MTUNE-SIFIVE7-64 %s
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// MTUNE-SIFIVE7-64: "-tune-cpu" "sifive-7-rv64"
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// Check mtune alias CPU has resolved to the right CPU according XLEN.
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// RUN: %clang -target riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s
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// MTUNE-GENERIC-32: "-tune-cpu" "generic-rv32"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-64 %s
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// MTUNE-GENERIC-64: "-tune-cpu" "generic-rv64"
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// RUN: %clang -target riscv32 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-32 %s
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// MTUNE-ROCKET-32: "-tune-cpu" "rocket-rv32"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s
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// MTUNE-ROCKET-64: "-tune-cpu" "rocket-rv64"
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// RUN: %clang -target riscv32 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-32 %s
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// MTUNE-SIFIVE7-SERIES-32: "-tune-cpu" "sifive-7-rv32"
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
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// MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
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// mcpu with default march
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s
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// MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
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@ -47,6 +78,20 @@
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// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c"
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// MCPU-MARCH: "-target-abi" "ilp32"
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// Check interaction between mcpu and mtune, mtune won't affect arch related
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// target feature, but mcpu will.
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//
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// In this case, sifive-e31 is rv32imac, sifive-e76 is rv32imafc, so M-extension
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// should not enabled.
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//
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// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -mtune=sifive-e76 | FileCheck -check-prefix=MTUNE-E31-MCPU-E76 %s
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// MTUNE-E31-MCPU-E76: "-target-cpu" "sifive-e31"
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// MTUNE-E31-MCPU-E76-NOT: "-target-feature" "+f"
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// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+m"
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// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+a"
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// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+c"
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// MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
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// Check failed cases
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// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
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@ -197,3 +197,11 @@
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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-u54, sifive-u74
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76, generic, rocket, sifive-7-series
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-u54, sifive-u74, generic, rocket, sifive-7-series
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@ -1,3 +1,13 @@
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#ifndef PROC_ALIAS
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#define PROC_ALIAS(NAME, RV32, RV64)
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#endif
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PROC_ALIAS({"generic"}, {"generic-rv32"}, {"generic-rv64"})
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PROC_ALIAS({"rocket"}, {"rocket-rv32"}, {"rocket-rv64"})
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PROC_ALIAS({"sifive-7-series"}, {"sifive-7-rv32"}, {"sifive-7-rv64"})
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#undef PROC_ALIAS
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#ifndef PROC
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#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)
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#endif
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@ -160,10 +160,14 @@ enum FeatureKind : unsigned {
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};
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bool checkCPUKind(CPUKind Kind, bool IsRV64);
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bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);
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CPUKind parseCPUKind(StringRef CPU);
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CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
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StringRef getMArchFromMcpu(StringRef CPU);
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
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void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
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bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features);
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StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
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} // namespace RISCV
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@ -253,6 +253,12 @@ bool checkCPUKind(CPUKind Kind, bool IsRV64) {
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
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}
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bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
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if (Kind == CK_INVALID)
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return false;
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
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}
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CPUKind parseCPUKind(StringRef CPU) {
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return llvm::StringSwitch<CPUKind>(CPU)
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#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
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@ -260,6 +266,22 @@ CPUKind parseCPUKind(StringRef CPU) {
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.Default(CK_INVALID);
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}
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StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64) {
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return llvm::StringSwitch<StringRef>(TuneCPU)
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#define PROC_ALIAS(NAME, RV32, RV64) .Case(NAME, IsRV64 ? StringRef(RV64) : StringRef(RV32))
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#include "llvm/Support/RISCVTargetParser.def"
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.Default(TuneCPU);
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}
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CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) {
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TuneCPU = resolveTuneCPUAlias(TuneCPU, IsRV64);
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return llvm::StringSwitch<CPUKind>(TuneCPU)
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#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
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#include "llvm/Support/RISCVTargetParser.def"
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.Default(CK_INVALID);
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}
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StringRef getMArchFromMcpu(StringRef CPU) {
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CPUKind Kind = parseCPUKind(CPU);
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
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@ -272,6 +294,15 @@ void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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}
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}
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void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
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Values.emplace_back(C.Name);
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}
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#define PROC_ALIAS(NAME, RV32, RV64) Values.emplace_back(StringRef(NAME));
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#include "llvm/Support/RISCVTargetParser.def"
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}
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// Get all features except standard extension feature
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bool getCPUFeaturesExceptStdExt(CPUKind Kind,
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std::vector<StringRef> &Features) {
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@ -198,7 +198,9 @@ void RISCVAsmPrinter::emitAttributes() {
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StringRef CPU = TM.getTargetCPU();
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StringRef FS = TM.getTargetFeatureString();
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const RISCVTargetMachine &RTM = static_cast<const RISCVTargetMachine &>(TM);
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const RISCVSubtarget STI(TT, CPU, FS, /*ABIName=*/"", RTM);
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/* TuneCPU doesn't impact emission of ELF attributes, ELF attributes only
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care about arch related features, so we can set TuneCPU as CPU. */
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const RISCVSubtarget STI(TT, CPU, /*TuneCPU=*/CPU, FS, /*ABIName=*/"", RTM);
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RTS.emitTargetAttributes(STI);
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}
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@ -30,13 +30,16 @@ using namespace llvm;
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void RISCVSubtarget::anchor() {}
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RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
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const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
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const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
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// Determine default and user-specified characteristics
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bool Is64Bit = TT.isArch64Bit();
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std::string CPUName = std::string(CPU);
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std::string TuneCPUName = std::string(TuneCPU);
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if (CPUName.empty())
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CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
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ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
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if (TuneCPUName.empty())
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TuneCPUName = CPUName;
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ParseSubtargetFeatures(CPUName, TuneCPUName, FS);
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if (Is64Bit) {
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XLenVT = MVT::i64;
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XLen = 64;
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@ -47,11 +50,12 @@ RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
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return *this;
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}
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RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
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StringRef TuneCPU, StringRef FS,
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StringRef ABIName, const TargetMachine &TM)
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: RISCVGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
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: RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
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UserReservedRegister(RISCV::NUM_TARGET_REGS),
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FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
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FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
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InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
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CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
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Legalizer.reset(new RISCVLegalizerInfo(*this));
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@ -71,13 +71,15 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
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/// Initializes using the passed in CPU and feature strings so that we can
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/// use initializer lists for subtarget initialization.
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RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef CPU, StringRef FS,
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StringRef CPU,
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StringRef TuneCPU,
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StringRef FS,
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StringRef ABIName);
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public:
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// Initializes the data members to match that of the specified triple.
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RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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StringRef ABIName, const TargetMachine &TM);
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RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
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StringRef FS, StringRef ABIName, const TargetMachine &TM);
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// Parses features string setting specified subtarget options. The
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// definition of this function is auto-generated by tblgen.
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@ -75,13 +75,16 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
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const RISCVSubtarget *
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RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute TuneAttr = F.getFnAttribute("tune-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU =
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CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
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std::string TuneCPU =
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TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
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std::string FS =
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FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
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std::string Key = CPU + FS;
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std::string Key = CPU + TuneCPU + FS;
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auto &I = SubtargetMap[Key];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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@ -98,7 +101,7 @@ RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
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}
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ABIName = ModuleTargetABI->getString();
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}
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I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, FS, ABIName, *this);
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I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
|
||||
}
|
||||
return I.get();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue