forked from OSchip/llvm-project
[x86][icelake][vpclmulqdq]
added vpclmulqdq feature recognition added intrinsics support for vpclmulqdq instructions _mm256_clmulepi64_epi128 _mm512_clmulepi64_epi128 matching a similar work on the backend (D40101) Differential Revision: https://reviews.llvm.org/D41573 llvm-svn: 321480
This commit is contained in:
Coby Tayree
parent
6ec880d9b5
commit
cf96c876c6
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@ -453,6 +453,10 @@ TARGET_BUILTIN(__builtin_ia32_vgf2p8mulb_v64qi, "V64cV64cV64c", "", "avx512bw,gf
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// CLMUL
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TARGET_BUILTIN(__builtin_ia32_pclmulqdq128, "V2LLiV2LLiV2LLiIc", "", "pclmul")
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// VPCLMULQDQ
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TARGET_BUILTIN(__builtin_ia32_pclmulqdq256, "V4LLiV4LLiV4LLiIc", "", "vpclmulqdq")
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TARGET_BUILTIN(__builtin_ia32_pclmulqdq512, "V8LLiV8LLiV8LLiIc", "", "avx512f,vpclmulqdq")
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// AVX
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TARGET_BUILTIN(__builtin_ia32_addsubpd256, "V4dV4dV4d", "", "avx")
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TARGET_BUILTIN(__builtin_ia32_addsubps256, "V8fV8fV8f", "", "avx")
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@ -2547,6 +2547,8 @@ def mtbm : Flag<["-"], "mtbm">, Group<m_x86_Features_Group>;
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def mno_tbm : Flag<["-"], "mno-tbm">, Group<m_x86_Features_Group>;
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def mvaes : Flag<["-"], "mvaes">, Group<m_x86_Features_Group>;
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def mno_vaes : Flag<["-"], "mno-vaes">, Group<m_x86_Features_Group>;
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def mvpclmulqdq : Flag<["-"], "mvpclmulqdq">, Group<m_x86_Features_Group>;
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def mno_vpclmulqdq : Flag<["-"], "mno-vpclmulqdq">, Group<m_x86_Features_Group>;
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def mxop : Flag<["-"], "mxop">, Group<m_x86_Features_Group>;
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def mno_xop : Flag<["-"], "mno-xop">, Group<m_x86_Features_Group>;
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def mxsave : Flag<["-"], "mxsave">, Group<m_x86_Features_Group>;
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@ -134,6 +134,7 @@ bool X86TargetInfo::initFeatureMap(
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case CK_Icelake:
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setFeatureEnabledImpl(Features, "vaes", true);
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setFeatureEnabledImpl(Features, "gfni", true);
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setFeatureEnabledImpl(Features, "vpclmulqdq", true);
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// TODO: Add icelake features here.
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LLVM_FALLTHROUGH;
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case CK_Cannonlake:
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@ -462,7 +463,7 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
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LLVM_FALLTHROUGH;
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case AVX:
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Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
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Features["xsaveopt"] = Features["vaes"] = false;
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Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
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setXOPLevel(Features, FMA4, false);
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LLVM_FALLTHROUGH;
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case AVX2:
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@ -584,6 +585,13 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
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} else if (Name == "pclmul") {
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if (Enabled)
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setSSELevel(Features, SSE2, Enabled);
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else
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Features["vpclmulqdq"] = false;
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} else if (Name == "vpclmulqdq") {
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if (Enabled) {
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setSSELevel(Features, AVX, Enabled);
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Features["pclmul"] = true;
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}
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} else if (Name == "gfni") {
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if (Enabled)
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setSSELevel(Features, SSE2, Enabled);
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@ -652,6 +660,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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HasVAES = true;
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} else if (Feature == "+pclmul") {
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HasPCLMUL = true;
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} else if (Feature == "+vpclmulqdq") {
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HasVPCLMULQDQ = true;
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} else if (Feature == "+lzcnt") {
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HasLZCNT = true;
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} else if (Feature == "+rdrnd") {
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@ -956,6 +966,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
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if (HasPCLMUL)
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Builder.defineMacro("__PCLMUL__");
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if (HasVPCLMULQDQ)
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Builder.defineMacro("__VPCLMULQDQ__");
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if (HasLZCNT)
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Builder.defineMacro("__LZCNT__");
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@ -1209,6 +1222,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
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.Case("sse4a", true)
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.Case("tbm", true)
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.Case("vaes", true)
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.Case("vpclmulqdq", true)
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.Case("x87", true)
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.Case("xop", true)
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.Case("xsave", true)
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@ -1275,6 +1289,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
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.Case("sse4a", XOPLevel >= SSE4A)
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.Case("tbm", HasTBM)
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.Case("vaes", HasVAES)
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.Case("vpclmulqdq", HasVPCLMULQDQ)
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.Case("x86", true)
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.Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
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.Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
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@ -50,6 +50,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
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bool HasAES = false;
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bool HasVAES = false;
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bool HasPCLMUL = false;
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bool HasVPCLMULQDQ = false;
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bool HasGFNI = false;
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bool HasLZCNT = false;
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bool HasRDRND = false;
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@ -86,6 +86,7 @@ set(files
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vaesintrin.h
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varargs.h
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vecintrin.h
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vpclmulqdqintrin.h
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wmmintrin.h
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__wmmintrin_aes.h
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__wmmintrin_pclmul.h
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@ -118,6 +118,10 @@ _mm256_cvtph_ps(__m128i __a)
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}
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#endif /* __AVX2__ */
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#if !defined(_MSC_VER) || __has_feature(modules) || defined(__VPCLMULQDQ__)
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#include <vpclmulqdqintrin.h>
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#endif
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#if !defined(_MSC_VER) || __has_feature(modules) || defined(__BMI__)
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#include <bmiintrin.h>
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#endif
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@ -0,0 +1,42 @@
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/*===------------ vpclmulqdqintrin.h - VPCLMULQDQ intrinsics ---------------===
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <vpclmulqdqintrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef __VPCLMULQDQINTRIN_H
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#define __VPCLMULQDQINTRIN_H
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#define _mm256_clmulepi64_epi128(A, B, I) __extension__ ({ \
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(__m256i)__builtin_ia32_pclmulqdq256((__v4di)(__m256i)(A), \
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(__v4di)(__m256i)(B), \
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(char)(I)); })
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#define _mm512_clmulepi64_epi128(A, B, I) __extension__ ({ \
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(__m512i)__builtin_ia32_pclmulqdq512((__v8di)(__m512i)(A), \
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(__v8di)(__m512i)(B), \
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(char)(I)); })
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#endif // __VPCLMULQDQINTRIN_H
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@ -38,9 +38,9 @@ int __attribute__((target("arch=lakemont,mmx"))) lake(int a) { return 4; }
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// CHECK: lake{{.*}} #7
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// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+x87"
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// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
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// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-gfni,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-xop,-xsave,-xsaveopt"
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// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-gfni,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-xop,-xsave,-xsaveopt"
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// CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
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// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-xop,-xsave,-xsaveopt"
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// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop,-xsave,-xsaveopt"
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// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
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// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-3dnow,-3dnowa,-mmx"
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// CHECK: #7 = {{.*}}"target-cpu"="lakemont" "target-features"="+mmx"
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@ -0,0 +1,17 @@
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// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +vpclmulqdq -emit-llvm -o - | FileCheck %s --check-prefix AVX
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// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -DAVX512 -target-feature +vpclmulqdq -target-feature +avx512f -emit-llvm -o - | FileCheck %s --check-prefixes AVX,AVX512
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#include <immintrin.h>
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__m256i test_mm256_clmulepi64_epi128(__m256i A, __m256i B) {
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// AVX: @llvm.x86.pclmulqdq.256
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return _mm256_clmulepi64_epi128(A, B, 0);
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}
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#ifdef AVX512
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__m512i test_mm512_clmulepi64_epi128(__m512i A, __m512i B) {
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// AVX512: @llvm.x86.pclmulqdq.512
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return _mm512_clmulepi64_epi128(A, B, 0);
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}
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#endif
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@ -102,6 +102,17 @@
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mgfni %s -### -o %t.o 2>&1 | FileCheck -check-prefix=GFNI %s
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-gfni %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-GFNI %s
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<<<<<<<
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// GFNI: "-target-feature" "+gfni"
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// NO-GFNI: "-target-feature" "-gfni
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=======
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-clzero %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-CLZERO %s
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// CLZERO: "-target-feature" "+clzero"
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// NO-CLZERO: "-target-feature" "-clzero"
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mvpclmulqdq %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VPCLMULQDQ %s
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-vpclmulqdq %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VPCLMULQDQ %s
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// VPCLMULQDQ: "-target-feature" "+vpclmulqdq"
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// NO-VPCLMULQDQ: "-target-feature" "-vpclmulqdq"
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>>>>>>>
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@ -1081,6 +1081,7 @@
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// CHECK_ICL_M32: #define __SSE__ 1
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// CHECK_ICL_M32: #define __SSSE3__ 1
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// CHECK_ICL_M32: #define __VAES__ 1
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// CHECK_ICL_M32: #define __VPCLMULQDQ__ 1
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// CHECK_ICL_M32: #define __XSAVEC__ 1
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// CHECK_ICL_M32: #define __XSAVEOPT__ 1
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// CHECK_ICL_M32: #define __XSAVES__ 1
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@ -1128,6 +1129,7 @@
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// CHECK_ICL_M64: #define __SSE__ 1
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// CHECK_ICL_M64: #define __SSSE3__ 1
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// CHECK_ICL_M64: #define __VAES__ 1
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// CHECK_ICL_M64: #define __VPCLMULQDQ__ 1
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// CHECK_ICL_M64: #define __XSAVEC__ 1
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// CHECK_ICL_M64: #define __XSAVEOPT__ 1
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// CHECK_ICL_M64: #define __XSAVES__ 1
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// GFNI: #define __GFNI__ 1
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// GFNI: #define __SSE2__ 1
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// RUN: %clang -target i386-unknown-unknown -march=atom -mvpclmulqdq -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=VPCLMULQDQ %s
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// VPCLMULQDQ: #define __PCLMUL__ 1
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// VPCLMULQDQ: #define __VPCLMULQDQ__ 1
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// RUN: %clang -target i386-unknown-unknown -march=atom -mvpclmulqdq -mno-pclmul -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=VPCLMULQDQNOPCLMUL %s
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// VPCLMULQDQNOPCLMUL-NOT: #define __PCLMUL__ 1
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// VPCLMULQDQNOPCLMUL-NOT: #define __VPCLMULQDQ__ 1
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