forked from OSchip/llvm-project
[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with a FIXME: attached. This patch changes the handling of +t2dsp to be in line with other architecture extensions. Following a revert of r248152 and new review comments, this patch also includes renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc. The spelling of "t2dsp" is preserved, pending a further investigation of its possible external usage. Differential Revision: http://reviews.llvm.org/D12937 llvm-svn: 248519
This commit is contained in:
parent
299238a67b
commit
cf296444ab
llvm
include/llvm/Support
lib
Support
Target/ARM
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@ -61,35 +61,35 @@ ARM_ARCH("armv4t", AK_ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T,
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ARM_ARCH("armv5t", AK_ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T,
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AEK_NONE)
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ARM_ARCH("armv5te", AK_ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv5tej", AK_ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv6", AK_ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv6k", AK_ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv6t2", AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv6z", AK_ARMV6Z, "6Z", "v6z", ARMBuildAttrs::CPUArch::v6KZ,
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AEK_SEC)
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AEK_DSP)
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ARM_ARCH("armv6zk", AK_ARMV6ZK, "6ZK", "v6zk", ARMBuildAttrs::CPUArch::v6KZ,
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AEK_SEC)
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AEK_DSP)
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ARM_ARCH("armv6-m", AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M,
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AEK_NONE)
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ARM_ARCH("armv6s-m", AK_ARMV6SM, "6S-M", "v6sm", ARMBuildAttrs::CPUArch::v6S_M,
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AEK_NONE)
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ARM_ARCH("armv7-a", AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv7-r", AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7,
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AEK_HWDIV)
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(AEK_HWDIV | AEK_DSP))
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ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7,
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AEK_HWDIV)
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ARM_ARCH("armv7e-m", AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M,
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AEK_HWDIV)
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(AEK_HWDIV | AEK_DSP))
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ARM_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8,
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(AEK_SEC | AEK_MP | AEK_VIRT | AEK_HWDIVARM | AEK_HWDIV))
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(AEK_SEC | AEK_MP | AEK_VIRT | AEK_HWDIVARM | AEK_HWDIV | AEK_DSP))
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ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a", ARMBuildAttrs::CPUArch::v8,
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(AEK_SEC | AEK_MP | AEK_VIRT | AEK_HWDIVARM | AEK_HWDIV))
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(AEK_SEC | AEK_MP | AEK_VIRT | AEK_HWDIVARM | AEK_HWDIV | AEK_DSP))
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// Non-standard Arch names.
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ARM_ARCH("iwmmxt", AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE,
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AEK_NONE)
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@ -100,21 +100,21 @@ ARM_ARCH("xscale", AK_XSCALE, "xscale", "", ARMBuildAttrs::CPUArch::v5TE,
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ARM_ARCH("armv5", AK_ARMV5, "5T", "v5", ARMBuildAttrs::CPUArch::v5T,
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AEK_NONE)
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ARM_ARCH("armv5e", AK_ARMV5E, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv6j", AK_ARMV6J, "6J", "v6", ARMBuildAttrs::CPUArch::v6,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv6hl", AK_ARMV6HL, "6-M", "v6hl", ARMBuildAttrs::CPUArch::v6_M,
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AEK_NONE)
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ARM_ARCH("armv7", AK_ARMV7, "7", "v7", ARMBuildAttrs::CPUArch::v7,
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AEK_NONE)
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ARM_ARCH("armv7l", AK_ARMV7L, "7-L", "v7l", ARMBuildAttrs::CPUArch::v7,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv7hl", AK_ARMV7HL, "7-L", "v7hl", ARMBuildAttrs::CPUArch::v7,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv7s", AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7,
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AEK_NONE)
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AEK_DSP)
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ARM_ARCH("armv7k", AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7,
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AEK_NONE)
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AEK_DSP)
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#undef ARM_ARCH
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#ifndef ARM_ARCH_EXT_NAME
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@ -81,6 +81,7 @@ enum ArchExtKind : unsigned {
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AEK_SIMD = 0x80,
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AEK_SEC = 0x100,
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AEK_VIRT = 0x200,
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AEK_DSP = 0x400,
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// Unsupported extensions.
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AEK_OS = 0x8000000,
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AEK_IWMMXT = 0x10000000,
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@ -189,6 +189,11 @@ bool llvm::ARM::getExtensionFeatures(unsigned Extensions,
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else
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Features.push_back("-crc");
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if (Extensions & ARM::AEK_DSP)
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Features.push_back("+t2dsp");
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else
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Features.push_back("-t2dsp");
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return getHWDivFeatures(Extensions, Features);
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}
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@ -119,9 +119,9 @@ def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
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def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Has return address stack">;
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/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
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def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
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"Supports v7 DSP instructions in Thumb2">;
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/// DSP extension (called "t2dsp" for backwards compatibility only).
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def FeatureDSP : SubtargetFeature<"t2dsp", "HasDSP", "true",
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"Supports DSP instructions in ARM and/or Thumb2">;
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// Multiprocessing extension.
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def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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@ -279,9 +279,8 @@ def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
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"Cortex-R4 ARM processors",
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[FeatureHWDiv,
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FeatureAvoidPartialCPSR,
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FeatureDSPThumb2, FeatureT2XtPk,
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HasV7Ops, FeatureDB, FeatureHasRAS,
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FeatureRClass]>;
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FeatureDSP, FeatureT2XtPk, HasV7Ops,
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FeatureDB, FeatureHasRAS, FeatureRClass]>;
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def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
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"Cortex-R5 ARM processors",
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@ -369,55 +368,50 @@ def : Processor<"mpcore", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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// V6T2 Processors.
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def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
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FeatureDSPThumb2]>;
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def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, FeatureDSP]>;
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def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
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FeatureHasSlowFPVMLx,
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FeatureDSPThumb2]>;
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FeatureDSP]>;
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// V7a Processors.
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// FIXME: A5 has currently the same Schedule model as A8
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def : ProcessorModel<"cortex-a5", CortexA8Model,
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[ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureVFP4, FeatureDSPThumb2,
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FeatureVFP4, FeatureDSP,
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FeatureHasRAS, FeatureAClass]>;
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def : ProcessorModel<"cortex-a7", CortexA8Model,
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[ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS,
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FeatureAClass]>;
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FeatureDSP, FeatureHasRAS, FeatureAClass]>;
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def : ProcessorModel<"cortex-a8", CortexA8Model,
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[ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS,
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FeatureAClass]>;
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FeatureDSP, FeatureHasRAS, FeatureAClass]>;
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def : ProcessorModel<"cortex-a9", CortexA9Model,
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[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS, FeatureMP,
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FeatureDSP, FeatureHasRAS, FeatureMP,
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FeatureAClass]>;
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// FIXME: A12 has currently the same Schedule model as A9
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def : ProcessorModel<"cortex-a12", CortexA9Model,
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[ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureMP,
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FeatureDSP, FeatureMP,
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FeatureHasRAS, FeatureAClass]>;
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// FIXME: A15 has currently the same ProcessorModel as A9.
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def : ProcessorModel<"cortex-a15", CortexA9Model,
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[ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS,
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FeatureAClass]>;
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FeatureDSP, FeatureHasRAS, FeatureAClass]>;
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// FIXME: A17 has currently the same Schedule model as A9
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def : ProcessorModel<"cortex-a17", CortexA9Model,
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[ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureMP,
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FeatureDSP, FeatureMP,
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FeatureHasRAS, FeatureAClass]>;
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// FIXME: krait has currently the same Schedule model as A9
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def : ProcessorModel<"krait", CortexA9Model,
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[ProcKrait, HasV7Ops,
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FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS,
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FeatureAClass]>;
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FeatureDSP, FeatureHasRAS, FeatureAClass]>;
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// FIXME: R4 has currently the same ProcessorModel as A8.
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def : ProcessorModel<"cortex-r4", CortexA8Model,
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@ -432,14 +426,13 @@ def : ProcessorModel<"cortex-r4f", CortexA8Model,
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// FIXME: R5 has currently the same ProcessorModel as A8.
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def : ProcessorModel<"cortex-r5", CortexA8Model,
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[ProcR5, HasV7Ops, FeatureDB,
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FeatureVFP3, FeatureDSPThumb2,
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FeatureHasRAS,
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FeatureVFP3, FeatureDSP, FeatureHasRAS,
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FeatureD16, FeatureRClass]>;
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// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
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def : ProcessorModel<"cortex-r7", CortexA8Model,
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[ProcR5, HasV7Ops, FeatureDB,
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FeatureVFP3, FeatureDSPThumb2,
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FeatureVFP3, FeatureDSP,
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FeatureHasRAS, FeatureVFPOnlySP,
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FeatureD16, FeatureMP, FeatureRClass]>;
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@ -454,13 +447,12 @@ def : ProcNoItin<"sc300", [HasV7Ops,
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// V7EM Processors.
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def : ProcNoItin<"cortex-m4", [HasV7Ops,
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FeatureThumb2, FeatureNoARM, FeatureDB,
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FeatureHWDiv, FeatureDSPThumb2,
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FeatureT2XtPk, FeatureVFP4,
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FeatureVFPOnlySP, FeatureD16,
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FeatureHWDiv, FeatureDSP, FeatureT2XtPk,
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FeatureVFP4, FeatureVFPOnlySP, FeatureD16,
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FeatureMClass]>;
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def : ProcNoItin<"cortex-m7", [HasV7Ops,
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FeatureThumb2, FeatureNoARM, FeatureDB,
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FeatureHWDiv, FeatureDSPThumb2,
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FeatureHWDiv, FeatureDSP,
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FeatureT2XtPk, FeatureFPARMv8,
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FeatureD16, FeatureMClass]>;
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@ -468,26 +460,26 @@ def : ProcNoItin<"cortex-m7", [HasV7Ops,
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// Swift uArch Processors.
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def : ProcessorModel<"swift", SwiftModel,
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[ProcSwift, HasV7Ops, FeatureNEON,
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FeatureDB, FeatureDSPThumb2,
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FeatureDB, FeatureDSP,
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FeatureHasRAS, FeatureAClass]>;
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// V8 Processors
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def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
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FeatureDB, FeatureFPARMv8,
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FeatureNEON, FeatureDSPThumb2]>;
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FeatureNEON, FeatureDSP]>;
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def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
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FeatureDB, FeatureFPARMv8,
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FeatureNEON, FeatureDSPThumb2]>;
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FeatureNEON, FeatureDSP]>;
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// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
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def : ProcNoItin<"cortex-a72", [ProcA57, HasV8Ops, FeatureAClass,
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FeatureDB, FeatureFPARMv8,
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FeatureNEON, FeatureDSPThumb2]>;
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FeatureNEON, FeatureDSP]>;
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// Cyclone is very similar to swift
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def : ProcessorModel<"cyclone", SwiftModel,
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[ProcSwift, HasV8Ops, HasV7Ops,
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FeatureCrypto, FeatureFPARMv8,
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FeatureDB,FeatureDSPThumb2,
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FeatureDB, FeatureDSP,
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FeatureHasRAS, FeatureZCZeroing]>;
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//===----------------------------------------------------------------------===//
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@ -523,7 +523,7 @@ static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
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if (Subtarget->hasV8Ops())
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return ARMBuildAttrs::v8;
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else if (Subtarget->hasV7Ops()) {
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if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
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if (Subtarget->isMClass() && Subtarget->hasDSP())
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return ARMBuildAttrs::v7E_M;
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return ARMBuildAttrs::v7;
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} else if (Subtarget->hasV6T2Ops())
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@ -3442,9 +3442,9 @@ static inline int getMClassRegisterSYSmValueMask(StringRef RegString) {
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// The flags here are common to those allowed for apsr in the A class cores and
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// those allowed for the special registers in the M class cores. Returns a
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// value representing which flags were present, -1 if invalid.
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static inline int getMClassFlagsMask(StringRef Flags, bool hasThumb2DSP) {
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static inline int getMClassFlagsMask(StringRef Flags, bool hasDSP) {
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if (Flags.empty())
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return 0x2 | (int)hasThumb2DSP;
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return 0x2 | (int)hasDSP;
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return StringSwitch<int>(Flags)
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.Case("g", 0x1)
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@ -3473,7 +3473,7 @@ static int getMClassRegisterMask(StringRef Reg, StringRef Flags, bool IsRead,
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}
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// We know we are now handling a write so need to get the mask for the flags.
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int Mask = getMClassFlagsMask(Flags, Subtarget->hasThumb2DSP());
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int Mask = getMClassFlagsMask(Flags, Subtarget->hasDSP());
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// Only apsr, iapsr, eapsr, xpsr can have flags. The other register values
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// shouldn't have flags present.
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@ -3482,7 +3482,7 @@ static int getMClassRegisterMask(StringRef Reg, StringRef Flags, bool IsRead,
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// The _g and _nzcvqg versions are only valid if the DSP extension is
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// available.
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if (!Subtarget->hasThumb2DSP() && (Mask & 0x1))
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if (!Subtarget->hasDSP() && (Mask & 0x1))
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return -1;
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// The register was valid so need to put the mask in the correct place
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@ -697,7 +697,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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}
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if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
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|| (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
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|| (Subtarget->isThumb2() && !Subtarget->hasDSP()))
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setOperationAction(ISD::MULHS, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
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@ -234,9 +234,8 @@ def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
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def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
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AssemblerPredicate<"FeatureT2XtPk",
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"pack/extract">;
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def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
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AssemblerPredicate<"FeatureDSPThumb2",
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"thumb2-dsp">;
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def HasDSP : Predicate<"Subtarget->hasDSP()">,
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AssemblerPredicate<"FeatureDSP", "dsp">;
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def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
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AssemblerPredicate<"FeatureDB",
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"data-barriers">;
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@ -2100,7 +2100,7 @@ def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
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def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-24} = 0b010;
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let Inst{23} = 0b1;
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@ -2117,7 +2117,7 @@ class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
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dag iops = (ins rGPR:$Rn, rGPR:$Rm),
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string asm = "\t$Rd, $Rn, $Rm">
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: T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0101;
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let Inst{22-20} = op22_20;
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||||
|
@ -2215,13 +2215,13 @@ class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
|
|||
def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm),
|
||||
NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
|
||||
"usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
|
||||
// Signed/Unsigned saturate.
|
||||
class T2SatI<dag oops, dag iops, InstrItinClass itin,
|
||||
|
@ -2254,7 +2254,7 @@ def t2SSAT: T2SatI<
|
|||
def t2SSAT16: T2SatI<
|
||||
(outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
|
||||
"ssat16", "\t$Rd, $sat_imm, $Rn", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11110;
|
||||
let Inst{25-22} = 0b1100;
|
||||
let Inst{20} = 0;
|
||||
|
@ -2278,7 +2278,7 @@ def t2USAT: T2SatI<
|
|||
def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
|
||||
NoItinerary,
|
||||
"usat16", "\t$Rd, $sat_imm, $Rn", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-22} = 0b1111001110;
|
||||
let Inst{20} = 0;
|
||||
let Inst{15} = 0;
|
||||
|
@ -2605,7 +2605,7 @@ def t2UMAAL : T2MulLong<0b110, 0b0110,
|
|||
(outs rGPR:$RdLo, rGPR:$RdHi),
|
||||
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
|
||||
"umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
} // hasSideEffects
|
||||
|
||||
// Rounding variants of the below included for disassembly only
|
||||
|
@ -2614,7 +2614,7 @@ def t2UMAAL : T2MulLong<0b110, 0b0110,
|
|||
def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
|
||||
"smmul", "\t$Rd, $Rn, $Rm",
|
||||
[(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b101;
|
||||
|
@ -2624,7 +2624,7 @@ def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
|
|||
|
||||
def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
|
||||
"smmulr", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b101;
|
||||
|
@ -2636,7 +2636,7 @@ def t2SMMLA : T2FourReg<
|
|||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
|
||||
"smmla", "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b101;
|
||||
|
@ -2646,7 +2646,7 @@ def t2SMMLA : T2FourReg<
|
|||
def t2SMMLAR: T2FourReg<
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
|
||||
"smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b101;
|
||||
|
@ -2657,7 +2657,7 @@ def t2SMMLS: T2FourReg<
|
|||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
|
||||
"smmls", "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b110;
|
||||
|
@ -2667,7 +2667,7 @@ def t2SMMLS: T2FourReg<
|
|||
def t2SMMLSR:T2FourReg<
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
|
||||
"smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b110;
|
||||
|
@ -2679,7 +2679,7 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
|
|||
!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
|
||||
[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
|
||||
(sext_inreg rGPR:$Rm, i16)))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
|
@ -2692,7 +2692,7 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
|
|||
!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
|
||||
[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
|
||||
(sra rGPR:$Rm, (i32 16))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
|
@ -2705,7 +2705,7 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
|
|||
!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
|
||||
[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
|
||||
(sext_inreg rGPR:$Rm, i16)))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
|
@ -2718,7 +2718,7 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
|
|||
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
|
||||
[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
|
||||
(sra rGPR:$Rm, (i32 16))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
|
@ -2730,7 +2730,7 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
|
|||
def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
|
||||
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
|
||||
[]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b011;
|
||||
|
@ -2742,7 +2742,7 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
|
|||
def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
|
||||
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
|
||||
[]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b011;
|
||||
|
@ -2760,7 +2760,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
|||
[(set rGPR:$Rd, (add rGPR:$Ra,
|
||||
(opnode (sext_inreg rGPR:$Rn, i16),
|
||||
(sext_inreg rGPR:$Rm, i16))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
|
@ -2773,7 +2773,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
|||
!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
|
||||
(sra rGPR:$Rm, (i32 16)))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
|
@ -2786,7 +2786,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
|||
!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
|
||||
(sext_inreg rGPR:$Rm, i16))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
|
@ -2799,7 +2799,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
|||
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
|
||||
(sra rGPR:$Rm, (i32 16)))))]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
|
@ -2811,7 +2811,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
|||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b011;
|
||||
|
@ -2823,7 +2823,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
|
|||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b011;
|
||||
|
@ -2839,79 +2839,79 @@ defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
|||
def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
|
||||
// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
|
||||
def t2SMUAD: T2ThreeReg_mac<
|
||||
0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMUADX:T2ThreeReg_mac<
|
||||
0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMUSD: T2ThreeReg_mac<
|
||||
0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMUSDX:T2ThreeReg_mac<
|
||||
0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]> {
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMLAD : T2FourReg_mac<
|
||||
0, 0b010, 0b0000, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLADX : T2FourReg_mac<
|
||||
0, 0b010, 0b0001, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
|
||||
"\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
|
||||
"\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
|
||||
"\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
|
||||
"\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasThumb2DSP]>;
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Division Instructions.
|
||||
|
|
|
@ -147,7 +147,7 @@ void ARMSubtarget::initializeEnvironment() {
|
|||
HasCRC = false;
|
||||
HasZeroCycleZeroing = false;
|
||||
StrictAlign = false;
|
||||
Thumb2DSP = false;
|
||||
HasDSP = false;
|
||||
UseNaClTrap = false;
|
||||
GenLongCalls = false;
|
||||
UnsafeFPMath = false;
|
||||
|
|
|
@ -199,9 +199,9 @@ protected:
|
|||
/// blocks to conform to ARMv8 rule.
|
||||
bool RestrictIT;
|
||||
|
||||
/// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
|
||||
/// and such) instructions in Thumb2 code.
|
||||
bool Thumb2DSP;
|
||||
/// HasDSP - If true, the subtarget supports the DSP (saturating arith
|
||||
/// and such) instructions.
|
||||
bool HasDSP;
|
||||
|
||||
/// NaCl TRAP instruction is generated instead of the regular TRAP.
|
||||
bool UseNaClTrap;
|
||||
|
@ -343,7 +343,7 @@ public:
|
|||
bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
|
||||
bool hasRAS() const { return HasRAS; }
|
||||
bool hasMPExtension() const { return HasMPExtension; }
|
||||
bool hasThumb2DSP() const { return Thumb2DSP; }
|
||||
bool hasDSP() const { return HasDSP; }
|
||||
bool useNaClTrap() const { return UseNaClTrap; }
|
||||
bool genLongCalls() const { return GenLongCalls; }
|
||||
|
||||
|
|
|
@ -272,8 +272,8 @@ class ARMAsmParser : public MCTargetAsmParser {
|
|||
bool hasARM() const {
|
||||
return !STI.getFeatureBits()[ARM::FeatureNoARM];
|
||||
}
|
||||
bool hasThumb2DSP() const {
|
||||
return STI.getFeatureBits()[ARM::FeatureDSPThumb2];
|
||||
bool hasDSP() const {
|
||||
return STI.getFeatureBits()[ARM::FeatureDSP];
|
||||
}
|
||||
bool hasD16() const {
|
||||
return STI.getFeatureBits()[ARM::FeatureD16];
|
||||
|
@ -3972,7 +3972,7 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
|
|||
if (FlagsVal == ~0U)
|
||||
return MatchOperand_NoMatch;
|
||||
|
||||
if (!hasThumb2DSP() && (FlagsVal & 0x400))
|
||||
if (!hasDSP() && (FlagsVal & 0x400))
|
||||
// The _g and _nzcvqg versions are only valid if the DSP extension is
|
||||
// available.
|
||||
return MatchOperand_NoMatch;
|
||||
|
|
|
@ -4111,7 +4111,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
|
|||
// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
|
||||
// only if the processor includes the DSP extension.
|
||||
if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
|
||||
(!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
|
||||
(!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
|
||||
S = MCDisassembler::SoftFail;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -804,7 +804,7 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
|
|||
unsigned Opcode = MI->getOpcode();
|
||||
|
||||
// For writes, handle extended mask bits if the DSP extension is present.
|
||||
if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) {
|
||||
if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
|
||||
switch (SYSm) {
|
||||
case 0x400:
|
||||
O << "apsr_g";
|
||||
|
|
|
@ -141,7 +141,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
|
|||
llvm_unreachable("invalid sub-architecture for ARM");
|
||||
case Triple::ARMSubArch_v8:
|
||||
if (NoCPU)
|
||||
// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
|
||||
// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP,
|
||||
// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
|
||||
// FeatureT2XtPk, FeatureCrypto, FeatureCRC
|
||||
ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
|
||||
|
@ -152,7 +152,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
|
|||
break;
|
||||
case Triple::ARMSubArch_v8_1a:
|
||||
if (NoCPU)
|
||||
// v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
|
||||
// v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP,
|
||||
// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
|
||||
// FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a
|
||||
ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
|
||||
|
@ -172,7 +172,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
|
|||
break;
|
||||
case Triple::ARMSubArch_v7em:
|
||||
if (NoCPU)
|
||||
// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
|
||||
// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSP,
|
||||
// FeatureT2XtPk, FeatureMClass
|
||||
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
|
||||
else
|
||||
|
@ -181,7 +181,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
|
|||
break;
|
||||
case Triple::ARMSubArch_v7s:
|
||||
if (NoCPU)
|
||||
// v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
|
||||
// v7s: FeatureNEON, FeatureDB, FeatureDSP, FeatureHasRAS
|
||||
// Swift
|
||||
ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
|
||||
else
|
||||
|
@ -194,7 +194,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
|
|||
// the "minimum" feature set and use CPU string to figure out the exact
|
||||
// features.
|
||||
if (NoCPU)
|
||||
// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
|
||||
// v7a: FeatureNEON, FeatureDB, FeatureDSP, FeatureT2XtPk
|
||||
ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
|
||||
else
|
||||
// Use CPU to figure out the exact features.
|
||||
|
|
Loading…
Reference in New Issue