maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

R600/SI: Refactor DS instruction defs 

llvm-svn: 231683
This commit is contained in:
Tom Stellard 2015-03-09 18:49:45 +00:00
parent 028f8b43e2
commit cf051f4112
3 changed files with 121 additions and 179 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
llvm/lib/Target/R600/SIInstrFormats.td
View File

@ -577,6 +577,12 @@ class DS <dag outs, dag ins, string asm, list<dag> pattern> :
let DS = 1;
let UseNamedOperandTable = 1;
let DisableEncoding = "$m0";
// Most instruction load and store data, so set this as the default.
let mayLoad = 1;
let mayStore = 1;
let hasSideEffects = 0;
let SchedRW = [WriteLDS];
}

246
llvm/lib/Target/R600/SIInstrInfo.td
View File

@ -1483,10 +1483,8 @@ class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
DSe_vi <op>,
SIMCInstr <opName, SISubtarget.VI>;
class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
DS <outs, ins, asm, []>,
DSe <op>,
SIMCInstr <opName, SISubtarget.SI> {
class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
DS_Real_si <op,opName, outs, ins, asm> {
// Single load interpret the 2 i8imm operands as a single i16 offset.
bits<16> offset;
@ -1494,10 +1492,8 @@ class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
let offset1 = offset{15-8};
}
class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
DS <outs, ins, asm, []>,
DSe_vi <op>,
SIMCInstr <opName, SISubtarget.VI> {
class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
DS_Real_vi <op, opName, outs, ins, asm> {
// Single load interpret the 2 i8imm operands as a single i16 offset.
bits<16> offset;
@ -1505,181 +1501,113 @@ class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
let offset1 = offset{15-8};
}
multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
list<dag> pat> {
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
def "" : DS_Pseudo <opName, outs, ins, pat>;
multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
dag outs = (outs rc:$vdst),
dag ins = (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
string asm = opName#" $vdst, $addr"#"$offset"> {
let data0 = 0, data1 = 0 in {
def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
}
def "" : DS_Pseudo <opName, outs, ins, []>;
let data0 = 0, data1 = 0 in {
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
}
}
multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
: DS_1A_Load_m <
op,
asm,
(outs regClass:$vdst),
(ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
asm#" $vdst, $addr"#"$offset",
[]>;
multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
dag outs = (outs rc:$vdst),
dag ins = (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0,
ds_offset1:$offset1, M0Reg:$m0),
string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1"> {
multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
list<dag> pat> {
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
def "" : DS_Pseudo <opName, outs, ins, pat>;
def "" : DS_Pseudo <opName, outs, ins, []>;
let data0 = 0, data1 = 0 in {
def _si : DS_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
}
let data0 = 0, data1 = 0 in {
def _si : DS_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
}
}
multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
: DS_Load2_m <
op,
asm,
(outs regClass:$vdst),
(ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
M0Reg:$m0),
asm#" $vdst, $addr"#"$offset0"#"$offset1",
[]>;
multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
dag outs = (outs),
dag ins = (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset,
M0Reg:$m0),
string asm = opName#" $addr, $data0"#"$offset"> {
multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
string asm, list<dag> pat> {
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
def "" : DS_Pseudo <opName, outs, ins, pat>;
def "" : DS_Pseudo <opName, outs, ins, []>,
AtomicNoRet<opName, 0>;
let data1 = 0, vdst = 0 in {
def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
}
let data1 = 0, vdst = 0 in {
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
}
}
multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
: DS_1A_Store_m <
op,
asm,
(outs),
(ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
asm#" $addr, $data0"#"$offset",
[]>;
multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
dag outs = (outs),
dag ins = (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1,
ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"> {
multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
string asm, list<dag> pat> {
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
def "" : DS_Pseudo <opName, outs, ins, pat>;
def "" : DS_Pseudo <opName, outs, ins, []>;
let vdst = 0 in {
def _si : DS_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
}
let vdst = 0 in {
def _si : DS_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
}
}
multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
: DS_Store_m <
op,
asm,
(outs),
(ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
asm#" $addr, $data0, $data1"#"$offset0"#"$offset1",
[]>;
multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
string noRetOp = "",
dag outs = (outs rc:$vdst),
dag ins = (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset,
M0Reg:$m0),
string asm = opName#" $vdst, $addr, $data0"#"$offset"> {
// 1 address, 1 data.
multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
string asm, list<dag> pat, string noRetOp> {
let mayLoad = 1, mayStore = 1,
hasPostISelHook = 1 // Adjusted to no return version.
in {
def "" : DS_Pseudo <opName, outs, ins, pat>,
AtomicNoRet<noRetOp, 1>;
def "" : DS_Pseudo <opName, outs, ins, []>,
AtomicNoRet<noRetOp, 1>;
let data1 = 0 in {
def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
}
let data1 = 0 in {
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
}
}
multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
string noRetOp = ""> : DS_1A1D_RET_m <
op, asm,
(outs rc:$vdst),
(ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
asm#" $vdst, $addr, $data0"#"$offset", [], noRetOp>;
multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
string noRetOp = "", dag ins,
dag outs = (outs rc:$vdst),
string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"> {
// 1 address, 2 data.
multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
string asm, list<dag> pat, string noRetOp> {
let mayLoad = 1, mayStore = 1,
hasPostISelHook = 1 // Adjusted to no return version.
in {
def "" : DS_Pseudo <opName, outs, ins, pat>,
AtomicNoRet<noRetOp, 1>;
def "" : DS_Pseudo <opName, outs, ins, []>,
AtomicNoRet<noRetOp, 1>;
def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
}
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
}
multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
string noRetOp = "", RegisterClass src = rc> : DS_1A2D_RET_m <
op, asm,
(outs rc:$vdst),
(ins i1imm:$gds, VGPR_32:$addr, src:$data0, src:$data1, ds_offset:$offset, M0Reg:$m0),
asm#" $vdst, $addr, $data0, $data1"#"$offset",
[], noRetOp>;
string noRetOp = "", RegisterClass src = rc> :
DS_1A2D_RET_m <op, asm, rc, noRetOp,
(ins i1imm:$gds, VGPR_32:$addr, src:$data0, src:$data1,
ds_offset:$offset, M0Reg:$m0)
>;
// 1 address, 2 data.
multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
string asm, list<dag> pat, string noRetOp> {
let mayLoad = 1, mayStore = 1 in {
def "" : DS_Pseudo <opName, outs, ins, pat>,
AtomicNoRet<noRetOp, 0>;
multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
string noRetOp = opName,
dag outs = (outs),
dag ins = (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1,
ds_offset:$offset, M0Reg:$m0),
string asm = opName#" $addr, $data0, $data1"#"$offset"> {
let vdst = 0 in {
def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
}
def "" : DS_Pseudo <opName, outs, ins, []>,
AtomicNoRet<noRetOp, 0>;
let vdst = 0 in {
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
}
}
multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
string noRetOp = asm> : DS_1A2D_NORET_m <
op, asm,
(outs),
(ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
asm#" $addr, $data0, $data1"#"$offset",
[], noRetOp>;
// 1 address, 1 data.
multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
string asm, list<dag> pat, string noRetOp> {
let mayLoad = 1, mayStore = 1 in {
def "" : DS_Pseudo <opName, outs, ins, pat>,
AtomicNoRet<noRetOp, 0>;
let data1 = 0, vdst = 0 in {
def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
}
}
}
multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
string noRetOp = asm> : DS_1A1D_NORET_m <
op, asm,
(outs),
(ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
asm#" $addr, $data0"#"$offset",
[], noRetOp>;
multiclass DS_0A_RET <bits<8> op, string opName,
dag outs = (outs VGPR_32:$vdst),
dag ins = (ins i1imm:$gds, ds_offset:$offset, M0Reg:$m0),
@ -1689,8 +1617,8 @@ multiclass DS_0A_RET <bits<8> op, string opName,
def "" : DS_Pseudo <opName, outs, ins, []>;
let addr = 0, data0 = 0, data1 = 0 in {
def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
} // end addr = 0, data0 = 0, data1 = 0
} // end mayLoad = 1, mayStore = 1
}
@ -1700,14 +1628,12 @@ multiclass DS_1A_RET_GDS <bits<8> op, string opName,
dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
string asm = opName#" $vdst, $addr $offset"> {
let mayLoad = 1, mayStore = 1 in {
def "" : DS_Pseudo <opName, outs, ins, []>;
def "" : DS_Pseudo <opName, outs, ins, []>;
let data0 = 0, data1 = 0, gds = 1 in {
def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
} // end data0 = 0, data1 = 0, gds = 1
} // end mayLoad = 1, mayStore = 1
let data0 = 0, data1 = 0, gds = 1 in {
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
} // end data0 = 0, data1 = 0, gds = 1
}
multiclass DS_1A_GDS <bits<8> op, string opName,
@ -1732,8 +1658,8 @@ multiclass DS_1A <bits<8> op, string opName,
def "" : DS_Pseudo <opName, outs, ins, []>;
let vdst = 0, data0 = 0, data1 = 0 in {
def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
} // let vdst = 0, data0 = 0, data1 = 0
} // end mayLoad = 1, mayStore = 1
}

48
llvm/lib/Target/R600/SIInstructions.td
View File

@ -784,9 +784,11 @@ defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>;
defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>;
defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>;
defm DS_MSKOR_B32 : DS_1A2D_NORET <0xc, "ds_mskor_b32", VGPR_32>;
defm DS_WRITE_B32 : DS_Store_Helper <0xd, "ds_write_b32", VGPR_32>;
defm DS_WRITE2_B32 : DS_Store2_Helper <0xe, "ds_write2_b32", VGPR_32>;
defm DS_WRITE2ST64_B32 : DS_Store2_Helper <0xf, "ds_write2st64_b32", VGPR_32>;
let mayLoad = 0 in {
defm DS_WRITE_B32 : DS_1A1D_NORET <0xd, "ds_write_b32", VGPR_32>;
defm DS_WRITE2_B32 : DS_1A1D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>;
defm DS_WRITE2ST64_B32 : DS_1A1D_Off8_NORET <0xf, "ds_write2st64_b32", VGPR_32>;
}
defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>;
defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>;
defm DS_MIN_F32 : DS_1A2D_NORET <0x12, "ds_min_f32", VGPR_32>;
@ -797,8 +799,10 @@ defm DS_GWS_SEMA_V : DS_1A_GDS <0x1a, "ds_gws_sema_v">;
defm DS_GWS_SEMA_BR : DS_1A_GDS <0x1b, "ds_gws_sema_br">;
defm DS_GWS_SEMA_P : DS_1A_GDS <0x1c, "ds_gws_sema_p">;
defm DS_GWS_BARRIER : DS_1A_GDS <0x1d, "ds_gws_barrier">;
defm DS_WRITE_B8 : DS_Store_Helper <0x1e, "ds_write_b8", VGPR_32>;
defm DS_WRITE_B16 : DS_Store_Helper <0x1f, "ds_write_b16", VGPR_32>;
let mayLoad = 0 in {
defm DS_WRITE_B8 : DS_1A1D_NORET <0x1e, "ds_write_b8", VGPR_32>;
defm DS_WRITE_B16 : DS_1A1D_NORET <0x1f, "ds_write_b16", VGPR_32>;
}
defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
@ -826,14 +830,16 @@ defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32"
let SubtargetPredicate = isCI in {
defm DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f32">;
} // End isCI
defm DS_SWIZZLE_B32 : DS_Load_Helper <0x35, "ds_swizzle_b32", VGPR_32>;
defm DS_READ_B32 : DS_Load_Helper <0x36, "ds_read_b32", VGPR_32>;
defm DS_READ2_B32 : DS_Load2_Helper <0x37, "ds_read2_b32", VReg_64>;
defm DS_READ2ST64_B32 : DS_Load2_Helper <0x38, "ds_read2st64_b32", VReg_64>;
defm DS_READ_I8 : DS_Load_Helper <0x39, "ds_read_i8", VGPR_32>;
defm DS_READ_U8 : DS_Load_Helper <0x3a, "ds_read_u8", VGPR_32>;
defm DS_READ_I16 : DS_Load_Helper <0x3b, "ds_read_i16", VGPR_32>;
defm DS_READ_U16 : DS_Load_Helper <0x3c, "ds_read_u16", VGPR_32>;
defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>;
let mayStore = 0 in {
defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>;
defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>;
defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>;
defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>;
defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>;
defm DS_READ_I16 : DS_1A_RET <0x3b, "ds_read_i16", VGPR_32>;
defm DS_READ_U16 : DS_1A_RET <0x3c, "ds_read_u16", VGPR_32>;
}
defm DS_CONSUME : DS_0A_RET <0x3d, "ds_consume">;
defm DS_APPEND : DS_0A_RET <0x3e, "ds_append">;
defm DS_ORDERED_COUNT : DS_1A_RET_GDS <0x3f, "ds_ordered_count">;
@ -850,9 +856,11 @@ defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>;
defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>;
defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>;
defm DS_MSKOR_B64 : DS_1A2D_NORET <0x4c, "ds_mskor_b64", VReg_64>;
defm DS_WRITE_B64 : DS_Store_Helper <0x4d, "ds_write_b64", VReg_64>;
defm DS_WRITE2_B64 : DS_Store2_Helper <0x4E, "ds_write2_b64", VReg_64>;
defm DS_WRITE2ST64_B64 : DS_Store2_Helper <0x4f, "ds_write2st64_b64", VReg_64>;
let mayLoad = 0 in {
defm DS_WRITE_B64 : DS_1A1D_NORET <0x4d, "ds_write_b64", VReg_64>;
defm DS_WRITE2_B64 : DS_1A1D_Off8_NORET <0x4E, "ds_write2_b64", VReg_64>;
defm DS_WRITE2ST64_B64 : DS_1A1D_Off8_NORET <0x4f, "ds_write2st64_b64", VReg_64>;
}
defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>;
defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>;
defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>;
@ -879,9 +887,11 @@ defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmps
defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">;
defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">;
defm DS_READ_B64 : DS_Load_Helper <0x76, "ds_read_b64", VReg_64>;
defm DS_READ2_B64 : DS_Load2_Helper <0x77, "ds_read2_b64", VReg_128>;
defm DS_READ2ST64_B64 : DS_Load2_Helper <0x78, "ds_read2st64_b64", VReg_128>;
let mayStore = 0 in {
defm DS_READ_B64 : DS_1A_RET <0x76, "ds_read_b64", VReg_64>;
defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>;
defm DS_READ2ST64_B64 : DS_1A_Off8_RET <0x78, "ds_read2st64_b64", VReg_128>;
}
defm DS_ADD_SRC2_U32 : DS_1A <0x80, "ds_add_src2_u32">;
defm DS_SUB_SRC2_U32 : DS_1A <0x81, "ds_sub_src2_u32">;