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Make FGR64RegisterClass available if target is Mips64. 

llvm-svn: 140397
This commit is contained in:
Akira Hatanaka 2011-09-23 18:28:39 +00:00
parent 3aa2889cc7
commit ceb55e72de
1 changed files with 6 additions and 1 deletions
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7
llvm/lib/Target/Mips/MipsISelLowering.cpp
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@ -84,6 +84,7 @@ MipsTargetLowering::
MipsTargetLowering(MipsTargetMachine &TM) MipsTargetLowering(MipsTargetMachine &TM)
: TargetLowering(TM, new MipsTargetObjectFile()) { : TargetLowering(TM, new MipsTargetObjectFile()) {
Subtarget = &TM.getSubtarget<MipsSubtarget>(); Subtarget = &TM.getSubtarget<MipsSubtarget>();
bool HasMips64 = Subtarget->hasMips64();
// Mips does not have i1 type, so use i32 for // Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...). // setcc operations results (slt, sgt, ...).
@ -95,8 +96,12 @@ MipsTargetLowering(MipsTargetMachine &TM)
addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
// When dealing with single precision only, use libcalls // When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat()) if (!Subtarget->isSingleFloat()) {
if (HasMips64)
addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
else
addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
}
// Load extented operations for i1 types must be promoted // Load extented operations for i1 types must be promoted
setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);