forked from OSchip/llvm-project
[X86][SNB] Minor scheduler cleanup
Merge 2 instregex and explain the VMOVDQArr/MOVDQArr difference llvm-svn: 332591
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@ -512,9 +512,7 @@ def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
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"BTR(16|32|64)ri8",
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"BTR(16|32|64)rr",
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"BTS(16|32|64)ri8",
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"BTS(16|32|64)rr",
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"VMOVDQA(Y?)rr",
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"VMOVDQU(Y?)rr")>;
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"BTS(16|32|64)rr")>;
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def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
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let Latency = 1;
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@ -532,8 +530,7 @@ def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
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let ResourceCycles = [1];
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}
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def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr",
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"MOVDQArr", // TODO: Why are these separated from their VEX equivalent
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"MOVDQUrr")>; // TODO: Why are these separated from their VEX equivalent
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"MOVDQ(A|U)rr")>; // NOTE: Different port requirements to VEX equivalents
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def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
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let Latency = 2;
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@ -743,8 +740,7 @@ def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
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let NumMicroOps = 2;
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let ResourceCycles = [1,1];
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}
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def: InstRW<[SBWriteResGroup33], (instregex "PUSH64i8",
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"PUSH(16|32|64)r")>;
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def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>;
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def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
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let Latency = 5;
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