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[X86][AVX2] combineSetCCMOVMSK - handle all_of patterns for PMOVMSKB(PACKSSBW(LO(X), HI(X))) 

In the sign splat case, we can fold PMOVMSKB(PACKSSBW(LO(X), HI(X))) -> PMOVMSKB(BITCAST_v32i8(X)) without introducing a signmask + comparison (which unlike for any_of won't fold into a single TEST).
This commit is contained in:
Simon Pilgrim 2020-06-07 21:08:35 +01:00
parent a25f5cd70c
commit ce677ef532
3 changed files with 11 additions and 12 deletions
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11
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -40297,13 +40297,13 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
// sign bits prior to the comparison with zero unless we know that
// the vXi16 splats the sign bit down to the lower i8 half.
// TODO: Handle all_of patterns.
if (IsAnyOf && Vec.getOpcode() == X86ISD::PACKSS && VecVT == MVT::v16i8) {
if (Vec.getOpcode() == X86ISD::PACKSS && VecVT == MVT::v16i8) {
SDValue VecOp0 = Vec.getOperand(0);
SDValue VecOp1 = Vec.getOperand(1);
bool SignExt0 = DAG.ComputeNumSignBits(VecOp0) > 8;
bool SignExt1 = DAG.ComputeNumSignBits(VecOp1) > 8;
// PMOVMSKB(PACKSSBW(X, undef)) -> PMOVMSKB(BITCAST_v16i8(X)) & 0xAAAA.
if (CmpBits == 8 && VecOp1.isUndef()) {
if (IsAnyOf && CmpBits == 8 && VecOp1.isUndef()) {
SDLoc DL(EFLAGS);
SDValue Result = DAG.getBitcast(MVT::v16i8, VecOp0);
Result = DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, Result);
@ -40322,16 +40322,19 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
VecOp1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
VecOp0.getOperand(0) == VecOp1.getOperand(0) &&
VecOp0.getConstantOperandAPInt(1) == 0 &&
VecOp1.getConstantOperandAPInt(1) == 8) {
VecOp1.getConstantOperandAPInt(1) == 8 &&
(IsAnyOf || (SignExt0 && SignExt1))) {
SDLoc DL(EFLAGS);
SDValue Result = DAG.getBitcast(MVT::v32i8, VecOp0.getOperand(0));
Result = DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, Result);
unsigned CmpMask = IsAnyOf ? 0 : 0xFFFFFFFF;
if (!SignExt0 || !SignExt1) {
assert(IsAnyOf && "Only perform v16i16 signmasks for any_of patterns");
Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
DAG.getConstant(0xAAAAAAAA, DL, MVT::i32));
}
return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Result,
DAG.getConstant(0, DL, MVT::i32));
DAG.getConstant(CmpMask, DL, MVT::i32));
}
}

6
llvm/test/CodeGen/X86/vector-compare-all_of.ll
View File

@ -1304,10 +1304,8 @@ define i1 @bool_reduction_v16i16(<16 x i16> %x, <16 x i16> %y) {
; AVX2-LABEL: bool_reduction_v16i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
; AVX2-NEXT: cmpw $-1, %ax
; AVX2-NEXT: vpmovmskb %ymm0, %eax
; AVX2-NEXT: cmpl $-1, %eax
; AVX2-NEXT: sete %al
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq

6
llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
View File

@ -1269,10 +1269,8 @@ define i1 @icmp_v16i16_v16i1(<16 x i16>) {
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
; AVX2-NEXT: cmpw $-1, %ax
; AVX2-NEXT: vpmovmskb %ymm0, %eax
; AVX2-NEXT: cmpl $-1, %eax
; AVX2-NEXT: sete %al
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq