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[RISCV] Use the 'si' lib call for (double (fp_to_sint/uint i32 X)) when F extension is enabled. 

D80526 added custom lowering to pick the si lib call on RV64, but this custom handling is only enabled when the F and D extension are both disabled. This prevents the si library call from being used for double when F is enabled but D is not.

This patch changes the behavior so we always enable the Custom hook on RV64 and decide in ReplaceNodeResults if we should emit a libcall based on whether the FP type should be softened or not.

Differential Revision: https://reviews.llvm.org/D90817
This commit is contained in:
Craig Topper 2020-11-05 10:07:03 -08:00
parent f738aee0bb
commit ce5f4f22e9
2 changed files with 12 additions and 6 deletions
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10
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -212,8 +212,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setTruncStoreAction(MVT::f64, MVT::f16, Expand);
}
if (Subtarget.is64Bit() &&
!(Subtarget.hasStdExtD() || Subtarget.hasStdExtF())) {
if (Subtarget.is64Bit()) {
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
@ -941,6 +940,13 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0);
// If the FP type needs to be softened, emit a library call using the 'si'
// version. If we left it to default legalization we'd end up with 'di'. If
// the FP type doesn't need to be softened just let generic type
// legalization promote the result type.
if (getTypeAction(*DAG.getContext(), Op0.getValueType()) !=
TargetLowering::TypeSoftenFloat)
return;
RTLIB::Libcall LC;
if (N->getOpcode() == ISD::FP_TO_SINT ||
N->getOpcode() == ISD::STRICT_FP_TO_SINT)

8
llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
View File

@ -21,7 +21,7 @@ define i32 @fp64_to_ui32(double %a) nounwind {
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: call __fixunsdfdi
; RV64IF-NEXT: call __fixunsdfsi
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
@ -44,7 +44,7 @@ define i32 @fp64_to_si32(double %a) nounwind {
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: call __fixdfdi
; RV64IF-NEXT: call __fixdfsi
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
@ -72,7 +72,7 @@ define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: call __fixunsdfdi
; RV64IF-NEXT: call __fixunsdfsi
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
@ -95,7 +95,7 @@ define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: call __fixdfdi
; RV64IF-NEXT: call __fixdfsi
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret