forked from OSchip/llvm-project
parent
f9371d821f
commit
ce55eab936
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@ -1222,7 +1222,7 @@ multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
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(_.VT (OpNode SrcRC:$src))>, T8PD, EVEX;
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}
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multiclass avx512_int_broadcastbw_reg<bits<8> opc, string Name,
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multiclass avx512_int_broadcastbw_reg<bits<8> opc, string Name,
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X86VectorVTInfo _, SDPatternOperator OpNode,
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RegisterClass SrcRC, SubRegIndex Subreg> {
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let hasSideEffects = 0, ExeDomain = _.ExeDomain in
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@ -1250,7 +1250,7 @@ multiclass avx512_int_broadcastbw_reg_vl<bits<8> opc, string Name,
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AVX512VLVectorVTInfo _, SDPatternOperator OpNode,
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RegisterClass SrcRC, SubRegIndex Subreg, Predicate prd> {
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let Predicates = [prd] in
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defm Z : avx512_int_broadcastbw_reg<opc, Name#Z, _.info512, OpNode, SrcRC,
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defm Z : avx512_int_broadcastbw_reg<opc, Name#Z, _.info512, OpNode, SrcRC,
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Subreg>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_int_broadcastbw_reg<opc, Name#Z256, _.info256, OpNode,
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