forked from OSchip/llvm-project
[libunwind] Add support for OpenRISC 1000.
This patch makes no assumptions on ABI past the ABI defined in the OpenRISC 1000 spec except that the DWARF register numbers will be 0-31 for registers r0-r31, which is true for both gcc and clang at the moment. llvm-svn: 246413
This commit is contained in:
Peter Zotov
parent
afeac301b1
commit
ce4c5c9849
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@ -497,4 +497,40 @@ enum {
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// 8192-16383 -- Unspecified vendor co-processor register.
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};
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// OpenRISC1000 register numbers
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enum {
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UNW_OR1K_R0 = 0,
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UNW_OR1K_R1 = 1,
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UNW_OR1K_R2 = 2,
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UNW_OR1K_R3 = 3,
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UNW_OR1K_R4 = 4,
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UNW_OR1K_R5 = 5,
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UNW_OR1K_R6 = 6,
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UNW_OR1K_R7 = 7,
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UNW_OR1K_R8 = 8,
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UNW_OR1K_R9 = 9,
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UNW_OR1K_R10 = 10,
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UNW_OR1K_R11 = 11,
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UNW_OR1K_R12 = 12,
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UNW_OR1K_R13 = 13,
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UNW_OR1K_R14 = 14,
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UNW_OR1K_R15 = 15,
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UNW_OR1K_R16 = 16,
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UNW_OR1K_R17 = 17,
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UNW_OR1K_R18 = 18,
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UNW_OR1K_R19 = 19,
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UNW_OR1K_R20 = 20,
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UNW_OR1K_R21 = 21,
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UNW_OR1K_R22 = 22,
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UNW_OR1K_R23 = 23,
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UNW_OR1K_R24 = 24,
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UNW_OR1K_R25 = 25,
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UNW_OR1K_R26 = 26,
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UNW_OR1K_R27 = 27,
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UNW_OR1K_R28 = 28,
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UNW_OR1K_R29 = 29,
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UNW_OR1K_R30 = 30,
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UNW_OR1K_R31 = 31,
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};
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#endif
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@ -1711,7 +1711,187 @@ inline v128 Registers_arm::getVectorRegister(int) const {
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inline void Registers_arm::setVectorRegister(int, v128) {
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_LIBUNWIND_ABORT("ARM vector support not implemented");
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}
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/// Registers_or1k holds the register state of a thread in an OpenRISC1000
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/// process.
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class _LIBUNWIND_HIDDEN Registers_or1k {
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public:
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Registers_or1k();
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Registers_or1k(const void *registers);
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bool validRegister(int num) const;
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uint32_t getRegister(int num) const;
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void setRegister(int num, uint32_t value);
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bool validFloatRegister(int num) const;
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double getFloatRegister(int num) const;
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void setFloatRegister(int num, double value);
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bool validVectorRegister(int num) const;
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v128 getVectorRegister(int num) const;
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void setVectorRegister(int num, v128 value);
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const char *getRegisterName(int num);
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void jumpto();
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static int lastDwarfRegNum() { return 31; }
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uint64_t getSP() const { return _registers.__r[1]; }
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void setSP(uint32_t value) { _registers.__r[1] = value; }
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uint64_t getIP() const { return _registers.__r[9]; }
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void setIP(uint32_t value) { _registers.__r[9] = value; }
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private:
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struct or1k_thread_state_t {
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unsigned int __r[32];
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};
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or1k_thread_state_t _registers;
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};
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inline Registers_or1k::Registers_or1k(const void *registers) {
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static_assert(sizeof(Registers_or1k) < sizeof(unw_context_t),
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"or1k registers do not fit into unw_context_t");
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memcpy(&_registers, static_cast<const uint8_t *>(registers),
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sizeof(_registers));
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}
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inline Registers_or1k::Registers_or1k() {
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memset(&_registers, 0, sizeof(_registers));
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}
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inline bool Registers_or1k::validRegister(int regNum) const {
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if (regNum == UNW_REG_IP)
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return true;
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if (regNum == UNW_REG_SP)
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return true;
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if (regNum < 0)
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return false;
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if (regNum <= UNW_OR1K_R31)
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return true;
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return false;
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}
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inline uint32_t Registers_or1k::getRegister(int regNum) const {
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if (regNum >= UNW_OR1K_R0 && regNum <= UNW_OR1K_R31)
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return _registers.__r[regNum - UNW_OR1K_R0];
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switch (regNum) {
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case UNW_REG_IP:
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return _registers.__r[9];
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case UNW_REG_SP:
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return _registers.__r[1];
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}
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_LIBUNWIND_ABORT("unsupported or1k register");
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}
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inline void Registers_or1k::setRegister(int regNum, uint32_t value) {
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if (regNum >= UNW_OR1K_R0 && regNum <= UNW_OR1K_R31) {
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_registers.__r[regNum - UNW_OR1K_R0] = value;
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return;
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}
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switch (regNum) {
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case UNW_REG_IP:
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_registers.__r[9] = value;
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return;
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case UNW_REG_SP:
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_registers.__r[1] = value;
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return;
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}
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_LIBUNWIND_ABORT("unsupported or1k register");
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}
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inline bool Registers_or1k::validFloatRegister(int regNum) const {
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return false;
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}
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inline double Registers_or1k::getFloatRegister(int regNum) const {
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_LIBUNWIND_ABORT("or1k float support not implemented");
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}
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inline void Registers_or1k::setFloatRegister(int regNum, double value) {
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_LIBUNWIND_ABORT("or1k float support not implemented");
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}
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inline bool Registers_or1k::validVectorRegister(int regNum) const {
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return false;
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}
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inline v128 Registers_or1k::getVectorRegister(int regNum) const {
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_LIBUNWIND_ABORT("or1k vector support not implemented");
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}
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inline void Registers_or1k::setVectorRegister(int regNum, v128 value) {
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_LIBUNWIND_ABORT("or1k vector support not implemented");
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}
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inline const char *Registers_or1k::getRegisterName(int regNum) {
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switch (regNum) {
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case UNW_OR1K_R0:
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return "r0";
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case UNW_OR1K_R1:
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return "r1";
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case UNW_OR1K_R2:
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return "r2";
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case UNW_OR1K_R3:
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return "r3";
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case UNW_OR1K_R4:
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return "r4";
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case UNW_OR1K_R5:
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return "r5";
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case UNW_OR1K_R6:
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return "r6";
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case UNW_OR1K_R7:
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return "r7";
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case UNW_OR1K_R8:
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return "r8";
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case UNW_OR1K_R9:
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return "r9";
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case UNW_OR1K_R10:
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return "r10";
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case UNW_OR1K_R11:
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return "r11";
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case UNW_OR1K_R12:
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return "r12";
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case UNW_OR1K_R13:
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return "r13";
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case UNW_OR1K_R14:
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return "r14";
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case UNW_OR1K_R15:
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return "r15";
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case UNW_OR1K_R16:
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return "r16";
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case UNW_OR1K_R17:
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return "r17";
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case UNW_OR1K_R18:
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return "r18";
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case UNW_OR1K_R19:
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return "r19";
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case UNW_OR1K_R20:
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return "r20";
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case UNW_OR1K_R21:
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return "r21";
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case UNW_OR1K_R22:
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return "r22";
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case UNW_OR1K_R23:
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return "r23";
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case UNW_OR1K_R24:
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return "r24";
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case UNW_OR1K_R25:
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return "r25";
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case UNW_OR1K_R26:
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return "r26";
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case UNW_OR1K_R27:
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return "r27";
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case UNW_OR1K_R28:
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return "r28";
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case UNW_OR1K_R29:
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return "r29";
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case UNW_OR1K_R30:
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return "r30";
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case UNW_OR1K_R31:
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return "r31";
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default:
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return "unknown register";
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}
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}
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} // namespace libunwind
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#endif // __REGISTERS_HPP__
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@ -556,6 +556,10 @@ private:
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compact_unwind_encoding_t dwarfEncoding(Registers_arm64 &) const {
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return UNWIND_ARM64_MODE_DWARF;
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}
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compact_unwind_encoding_t dwarfEncoding(Registers_or1k &) const {
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return 0;
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}
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#endif // _LIBUNWIND_SUPPORT_DWARF_UNWIND
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@ -427,4 +427,55 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreiWMMXCont
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#endif
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JMP(lr)
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#elif defined(__or1k__)
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DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv)
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#
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# void libunwind::Registers_or1k::jumpto()
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#
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# On entry:
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# thread_state pointer is in r3
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#
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# restore integral registerrs
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l.lwz r0, 0(r3)
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l.lwz r1, 4(r3)
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l.lwz r2, 8(r3)
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# skip r3 for now
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l.lwz r4, 16(r3)
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l.lwz r5, 20(r3)
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l.lwz r6, 24(r3)
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l.lwz r7, 28(r3)
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l.lwz r8, 32(r3)
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l.lwz r9, 36(r3)
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l.lwz r10, 40(r3)
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l.lwz r11, 44(r3)
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l.lwz r12, 48(r3)
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l.lwz r13, 52(r3)
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l.lwz r14, 56(r3)
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l.lwz r15, 60(r3)
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l.lwz r16, 64(r3)
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l.lwz r17, 68(r3)
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l.lwz r18, 72(r3)
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l.lwz r19, 76(r3)
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l.lwz r20, 80(r3)
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l.lwz r21, 84(r3)
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l.lwz r22, 88(r3)
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l.lwz r23, 92(r3)
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l.lwz r24, 96(r3)
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l.lwz r25,100(r3)
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l.lwz r26,104(r3)
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l.lwz r27,108(r3)
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l.lwz r28,112(r3)
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l.lwz r29,116(r3)
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l.lwz r30,120(r3)
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l.lwz r31,124(r3)
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# at last, restore r3
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l.lwz r3, 12(r3)
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# jump to pc
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l.jr r9
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l.nop
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#endif
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@ -413,4 +413,45 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveiWMMXControl
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#endif
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JMP(lr)
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#elif defined(__or1k__)
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#
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# extern int unw_getcontext(unw_context_t* thread_state)
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#
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# On entry:
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# thread_state pointer is in r3
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#
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DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
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l.sw 0(r3), r0
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l.sw 4(r3), r1
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l.sw 8(r3), r2
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l.sw 12(r3), r3
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l.sw 16(r3), r4
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l.sw 20(r3), r5
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l.sw 24(r3), r6
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l.sw 28(r3), r7
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l.sw 32(r3), r8
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l.sw 36(r3), r9
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l.sw 40(r3), r10
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l.sw 44(r3), r11
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l.sw 48(r3), r12
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l.sw 52(r3), r13
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l.sw 56(r3), r14
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l.sw 60(r3), r15
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l.sw 64(r3), r16
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l.sw 68(r3), r17
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l.sw 72(r3), r18
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l.sw 76(r3), r19
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l.sw 80(r3), r20
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l.sw 84(r3), r21
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l.sw 88(r3), r22
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l.sw 92(r3), r23
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l.sw 96(r3), r24
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l.sw 100(r3), r25
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l.sw 104(r3), r26
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l.sw 108(r3), r27
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l.sw 112(r3), r28
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l.sw 116(r3), r29
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l.sw 120(r3), r30
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l.sw 124(r3), r31
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#endif
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@ -61,6 +61,9 @@ _LIBUNWIND_EXPORT int unw_init_local(unw_cursor_t *cursor,
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#elif _LIBUNWIND_ARM_EHABI
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new ((void *)cursor) UnwindCursor<LocalAddressSpace, Registers_arm>(
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context, LocalAddressSpace::sThisAddressSpace);
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#elif defined(__or1k__)
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new ((void *)cursor) UnwindCursor<LocalAddressSpace, Registers_or1k>(
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context, LocalAddressSpace::sThisAddressSpace);
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#else
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#error Architecture not supported
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#endif
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