forked from OSchip/llvm-project
[AMDGPU] removed dead code handling rmw in memory legalizer
It was always using cmpxchg path and in rmw and cmpxchg instructions are not distinguishable in the BE. Differential Revision: https://reviews.llvm.org/D42976 llvm-svn: 324383
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@ -105,14 +105,10 @@ public:
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/// "None" otherwise.
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static Optional<SIMemOpInfo> getAtomicFenceInfo(
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const MachineBasicBlock::iterator &MI);
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/// \returns Atomic cmpxchg info if \p MI is an atomic cmpxchg operation,
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/// "None" otherwise.
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/// \returns Atomic cmpxchg/rmw info if \p MI is an atomic cmpxchg or
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/// rmw operation, "None" otherwise.
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static Optional<SIMemOpInfo> getAtomicCmpxchgInfo(
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const MachineBasicBlock::iterator &MI);
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/// \returns Atomic rmw info if \p MI is an atomic rmw operation,
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/// "None" otherwise.
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static Optional<SIMemOpInfo> getAtomicRmwInfo(
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const MachineBasicBlock::iterator &MI);
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/// \brief Reports unknown synchronization scope used in \p MI to LLVM
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/// context.
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@ -190,14 +186,10 @@ private:
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/// instructions are added/deleted or \p MI is modified, false otherwise.
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bool expandAtomicFence(const SIMemOpInfo &MOI,
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MachineBasicBlock::iterator &MI);
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/// \brief Expands atomic cmpxchg operation \p MI. Returns true if
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/// \brief Expands atomic cmpxchg or rmw operation \p MI. Returns true if
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/// instructions are added/deleted or \p MI is modified, false otherwise.
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bool expandAtomicCmpxchg(const SIMemOpInfo &MOI,
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MachineBasicBlock::iterator &MI);
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/// \brief Expands atomic rmw operation \p MI. Returns true if
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/// instructions are added/deleted or \p MI is modified, false otherwise.
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bool expandAtomicRmw(const SIMemOpInfo &MOI,
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MachineBasicBlock::iterator &MI);
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public:
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static char ID;
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@ -321,22 +313,6 @@ Optional<SIMemOpInfo> SIMemOpInfo::getAtomicCmpxchgInfo(
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return SIMemOpInfo::constructFromMIWithMMO(MI);
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}
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/* static */
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Optional<SIMemOpInfo> SIMemOpInfo::getAtomicRmwInfo(
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const MachineBasicBlock::iterator &MI) {
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assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
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if (!(MI->mayLoad() && MI->mayStore()))
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return None;
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// Be conservative if there are no memory operands.
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if (MI->getNumMemOperands() == 0)
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return SIMemOpInfo(SyncScope::System,
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AtomicOrdering::SequentiallyConsistent);
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return SIMemOpInfo::constructFromMIWithMMO(MI);
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}
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/* static */
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void SIMemOpInfo::reportUnknownSyncScope(
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const MachineBasicBlock::iterator &MI) {
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@ -546,43 +522,6 @@ bool SIMemoryLegalizer::expandAtomicCmpxchg(const SIMemOpInfo &MOI,
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return Changed;
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}
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bool SIMemoryLegalizer::expandAtomicRmw(const SIMemOpInfo &MOI,
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MachineBasicBlock::iterator &MI) {
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assert(MI->mayLoad() && MI->mayStore());
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bool Changed = false;
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if (MOI.isAtomic()) {
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if (MOI.getSSID() == SyncScope::System ||
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MOI.getSSID() == MMI->getAgentSSID()) {
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if (MOI.getOrdering() == AtomicOrdering::Release ||
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MOI.getOrdering() == AtomicOrdering::AcquireRelease ||
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MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent)
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Changed |= insertWaitcntVmcnt0(MI);
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if (MOI.getOrdering() == AtomicOrdering::Acquire ||
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MOI.getOrdering() == AtomicOrdering::AcquireRelease ||
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MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent) {
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Changed |= insertWaitcntVmcnt0(MI, false);
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Changed |= insertBufferWbinvl1Vol(MI, false);
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}
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return Changed;
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}
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if (MOI.getSSID() == SyncScope::SingleThread ||
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MOI.getSSID() == MMI->getWorkgroupSSID() ||
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MOI.getSSID() == MMI->getWavefrontSSID()) {
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Changed |= enableGLCBit(MI);
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return Changed;
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}
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llvm_unreachable("Unsupported synchronization scope");
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}
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return Changed;
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}
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bool SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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@ -609,8 +548,6 @@ bool SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) {
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Changed |= expandAtomicFence(MOI.getValue(), MI);
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else if (const auto &MOI = SIMemOpInfo::getAtomicCmpxchgInfo(MI))
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Changed |= expandAtomicCmpxchg(MOI.getValue(), MI);
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else if (const auto &MOI = SIMemOpInfo::getAtomicRmwInfo(MI))
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Changed |= expandAtomicRmw(MOI.getValue(), MI);
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}
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}
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