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[mips][msa] CHECK-DAG-ize MSA 2rf_int_float.ll test. 

No functional changes.

llvm-svn: 194390
This commit is contained in:
Matheus Almeida 2013-11-11 16:38:55 +00:00
parent fed22ad33b
commit ce207fa078
1 changed files with 50 additions and 30 deletions
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80
llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
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@ -18,9 +18,11 @@ entry:
declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind
; CHECK: llvm_mips_fclass_w_test:
; CHECK: ld.w
; CHECK: fclass.w
; CHECK: st.w
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_fclass_w_ARG1)
; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: fclass.w [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_fclass_w_RES)
; CHECK-DAG: st.w [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_fclass_w_test
;
@llvm_mips_fclass_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@ -37,9 +39,11 @@ entry:
declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind
; CHECK: llvm_mips_fclass_d_test:
; CHECK: ld.d
; CHECK: fclass.d
; CHECK: st.d
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_fclass_d_ARG1)
; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: fclass.d [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_fclass_d_RES)
; CHECK-DAG: st.d [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_fclass_d_test
;
@llvm_mips_ftrunc_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@ -56,9 +60,11 @@ entry:
declare <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float>) nounwind
; CHECK: llvm_mips_ftrunc_s_w_test:
; CHECK: ld.w
; CHECK: ftrunc_s.w
; CHECK: st.w
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_s_w_ARG1)
; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ftrunc_s.w [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_s_w_RES)
; CHECK-DAG: st.w [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_ftrunc_s_w_test
;
@llvm_mips_ftrunc_s_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@ -75,9 +81,11 @@ entry:
declare <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double>) nounwind
; CHECK: llvm_mips_ftrunc_s_d_test:
; CHECK: ld.d
; CHECK: ftrunc_s.d
; CHECK: st.d
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_s_d_ARG1)
; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ftrunc_s.d [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_s_d_RES)
; CHECK-DAG: st.d [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_ftrunc_s_d_test
;
@llvm_mips_ftrunc_u_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@ -94,9 +102,11 @@ entry:
declare <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float>) nounwind
; CHECK: llvm_mips_ftrunc_u_w_test:
; CHECK: ld.w
; CHECK: ftrunc_u.w
; CHECK: st.w
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_u_w_ARG1)
; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ftrunc_u.w [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_u_w_RES)
; CHECK-DAG: st.w [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_ftrunc_u_w_test
;
@llvm_mips_ftrunc_u_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@ -113,9 +123,11 @@ entry:
declare <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double>) nounwind
; CHECK: llvm_mips_ftrunc_u_d_test:
; CHECK: ld.d
; CHECK: ftrunc_u.d
; CHECK: st.d
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_u_d_ARG1)
; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ftrunc_u.d [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_u_d_RES)
; CHECK-DAG: st.d [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_ftrunc_u_d_test
;
@llvm_mips_ftint_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@ -132,9 +144,11 @@ entry:
declare <4 x i32> @llvm.mips.ftint.s.w(<4 x float>) nounwind
; CHECK: llvm_mips_ftint_s_w_test:
; CHECK: ld.w
; CHECK: ftint_s.w
; CHECK: st.w
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_s_w_ARG1)
; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ftint_s.w [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_s_w_RES)
; CHECK-DAG: st.w [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_ftint_s_w_test
;
@llvm_mips_ftint_s_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@ -151,9 +165,11 @@ entry:
declare <2 x i64> @llvm.mips.ftint.s.d(<2 x double>) nounwind
; CHECK: llvm_mips_ftint_s_d_test:
; CHECK: ld.d
; CHECK: ftint_s.d
; CHECK: st.d
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_s_d_ARG1)
; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ftint_s.d [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_s_d_RES)
; CHECK-DAG: st.d [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_ftint_s_d_test
;
@llvm_mips_ftint_u_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@ -170,9 +186,11 @@ entry:
declare <4 x i32> @llvm.mips.ftint.u.w(<4 x float>) nounwind
; CHECK: llvm_mips_ftint_u_w_test:
; CHECK: ld.w
; CHECK: ftint_u.w
; CHECK: st.w
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_u_w_ARG1)
; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ftint_u.w [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_u_w_RES)
; CHECK-DAG: st.w [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_ftint_u_w_test
;
@llvm_mips_ftint_u_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@ -189,8 +207,10 @@ entry:
declare <2 x i64> @llvm.mips.ftint.u.d(<2 x double>) nounwind
; CHECK: llvm_mips_ftint_u_d_test:
; CHECK: ld.d
; CHECK: ftint_u.d
; CHECK: st.d
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_u_d_ARG1)
; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ftint_u.d [[WD:\$w[0-9]+]], [[WS]]
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_u_d_RES)
; CHECK-DAG: st.d [[WD]], 0([[R2]])
; CHECK: .size llvm_mips_ftint_u_d_test
;