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[InstCombine] Regenerate and(srem(X,Pow2),C) test and add vector coverage

This commit is contained in:
Simon Pilgrim 2022-04-07 14:58:39 +01:00
parent edeceb8647
commit cde66d5ed1
1 changed files with 23 additions and 4 deletions
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27
llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll
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@ -1,9 +1,28 @@
; RUN: opt < %s -passes=instcombine -S | not grep rem
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
; PR2330
define i32 @a(i32 %b) nounwind {
; CHECK-LABEL: @a(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[B:%.*]], 1
; CHECK-NEXT: ret i32 [[TMP0]]
;
entry:
srem i32 %b, 8 ; <i32>:0 [#uses=1]
and i32 %0, 1 ; <i32>:1 [#uses=1]
ret i32 %1
srem i32 %b, 8 ; <i32>:0 [#uses=1]
and i32 %0, 1 ; <i32>:1 [#uses=1]
ret i32 %1
}
define <2 x i32> @a_vec(<2 x i32> %b) nounwind {
; CHECK-LABEL: @a_vec(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = srem <2 x i32> [[B:%.*]], <i32 8, i32 8>
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[TMP0]], <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i32> [[TMP1]]
;
entry:
srem <2 x i32> %b, <i32 8, i32 8>
and <2 x i32> %0, <i32 1, i32 1>
ret <2 x i32> %1
}