From cddde58f1c5d6956f669f690fb65920314f4e727 Mon Sep 17 00:00:00 2001 From: Sanjoy Das Date: Wed, 27 Jan 2016 17:05:09 +0000 Subject: [PATCH] [IndVars] Hoist DataLayout load out of loop; NFC llvm-svn: 258946 --- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp b/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp index b9d3bf5c4363..02c2629f6b5e 100644 --- a/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp +++ b/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp @@ -1783,6 +1783,7 @@ static PHINode *FindLoopCounter(Loop *L, const SCEV *BECount, const SCEV *BestInit = nullptr; BasicBlock *LatchBlock = L->getLoopLatch(); assert(LatchBlock && "needsLFTR should guarantee a loop latch"); + const DataLayout &DL = L->getHeader()->getModule()->getDataLayout(); for (BasicBlock::iterator I = L->getHeader()->begin(); isa(I); ++I) { PHINode *Phi = cast(I); @@ -1801,8 +1802,7 @@ static PHINode *FindLoopCounter(Loop *L, const SCEV *BECount, // AR may be wider than BECount. With eq/ne tests overflow is immaterial. // AR may not be a narrower type, or we may never exit. uint64_t PhiWidth = SE->getTypeSizeInBits(AR->getType()); - if (PhiWidth < BCWidth || - !L->getHeader()->getModule()->getDataLayout().isLegalInteger(PhiWidth)) + if (PhiWidth < BCWidth || !DL.isLegalInteger(PhiWidth)) continue; const SCEV *Step = dyn_cast(AR->getStepRecurrence(*SE));