forked from OSchip/llvm-project
[APInt] Use operator<<= where possible. NFC
llvm-svn: 301104
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parent
5f68af0806
commit
cdd5ae6676
llvm/lib
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@ -2323,8 +2323,8 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
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if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
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if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
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computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
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computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
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Depth + 1);
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Depth + 1);
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KnownZero = KnownZero << *ShAmt;
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KnownZero <<= *ShAmt;
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KnownOne = KnownOne << *ShAmt;
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KnownOne <<= *ShAmt;
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// Low bits are known zero.
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// Low bits are known zero.
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KnownZero.setLowBits(ShAmt->getZExtValue());
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KnownZero.setLowBits(ShAmt->getZExtValue());
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}
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}
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@ -1714,7 +1714,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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bestWidth = width;
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bestWidth = width;
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break;
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break;
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}
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}
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newMask = newMask << width;
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newMask <<= width;
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}
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}
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}
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}
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}
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}
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@ -26717,8 +26717,8 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
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DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1);
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DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1);
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unsigned ShAmt = ShiftImm->getZExtValue();
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unsigned ShAmt = ShiftImm->getZExtValue();
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if (Opc == X86ISD::VSHLI) {
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if (Opc == X86ISD::VSHLI) {
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KnownZero = KnownZero << ShAmt;
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KnownZero <<= ShAmt;
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KnownOne = KnownOne << ShAmt;
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KnownOne <<= ShAmt;
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// Low bits are known zero.
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// Low bits are known zero.
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KnownZero.setLowBits(ShAmt);
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KnownZero.setLowBits(ShAmt);
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} else {
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} else {
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