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Add AVX only vzeroall and vzeroupper instructions 

llvm-svn: 109002
This commit is contained in:
Bruno Cardoso Lopes 2010-07-21 08:56:24 +00:00
parent f97f626730
commit cdbec62510
3 changed files with 18 additions and 2 deletions
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6
llvm/lib/Target/X86/X86InstrSSE.td
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@ -5076,4 +5076,10 @@ def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>, VEX_4V; []>, VEX_4V;
// Zero All YMM registers
def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", []>, VEX, VEX_L;
// Zero Upper bits of YMM registers
def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", []>, VEX;
} // isAsmParserOnly } // isAsmParserOnly

6
llvm/lib/Target/X86/X86MCCodeEmitter.cpp
View File

@ -514,7 +514,10 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
VEX_X = 0x0; VEX_X = 0x0;
} }
break; break;
default: // MRMDestReg, MRM0r-MRM7r default: // MRMDestReg, MRM0r-MRM7r, RawFrm
if (!MI.getNumOperands())
break;
if (MI.getOperand(CurOp).isReg() && if (MI.getOperand(CurOp).isReg() &&
X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
VEX_B = 0; VEX_B = 0;
@ -530,7 +533,6 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
VEX_R = 0x0; VEX_R = 0x0;
} }
break; break;
assert(0 && "Not implemented!");
} }
// Emit segment override opcode prefix as needed. // Emit segment override opcode prefix as needed.

8
llvm/test/MC/AsmParser/X86/x86_32-encoding.s
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@ -13134,3 +13134,11 @@
// CHECK: encoding: [0xc4,0xe3,0x55,0x06,0x08,0x07] // CHECK: encoding: [0xc4,0xe3,0x55,0x06,0x08,0x07]
vperm2f128 $7, (%eax), %ymm5, %ymm1 vperm2f128 $7, (%eax), %ymm5, %ymm1
// CHECK: vzeroall
// CHECK: encoding: [0xc5,0xfc,0x77]
vzeroall
// CHECK: vzeroupper
// CHECK: encoding: [0xc5,0xf8,0x77]
vzeroupper