forked from OSchip/llvm-project
[Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.
llvm-svn: 227993
This commit is contained in:
Colin LeMahieu
parent
b60295a525
commit
cdba4e1bcc
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@ -628,6 +628,22 @@ def : Pat <(i32 (int_hexagon_C2_cmpltu (I32:$src1),
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(I32:$src2))),
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(i32 (C2_cmpgtu (I32:$src2), (I32:$src1)))>;
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/********************************************************************
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* ALU32/VH *
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*********************************************************************/
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// Vector add, subtract, average halfwords
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def: T_RR_pat<A2_svaddh, int_hexagon_A2_svaddh>;
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def: T_RR_pat<A2_svaddhs, int_hexagon_A2_svaddhs>;
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def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>;
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def: T_RR_pat<A2_svsubh, int_hexagon_A2_svsubh>;
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def: T_RR_pat<A2_svsubhs, int_hexagon_A2_svsubhs>;
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def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>;
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def: T_RR_pat<A2_svavgh, int_hexagon_A2_svavgh>;
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def: T_RR_pat<A2_svavghs, int_hexagon_A2_svavghs>;
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def: T_RR_pat<A2_svnavgh, int_hexagon_A2_svnavgh>;
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/********************************************************************
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* ALU64/ALU *
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*********************************************************************/
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@ -647,6 +663,83 @@ def: T_PP_pat<C2_cmpgtup, int_hexagon_C2_cmpgtup>;
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def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>;
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def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>;
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/********************************************************************
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* ALU64/VB *
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*********************************************************************/
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// ALU64 - Vector add
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def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddub>;
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def : T_PP_pat <A2_vaddubs, int_hexagon_A2_vaddubs>;
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def : T_PP_pat <A2_vaddh, int_hexagon_A2_vaddh>;
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def : T_PP_pat <A2_vaddhs, int_hexagon_A2_vaddhs>;
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def : T_PP_pat <A2_vadduhs, int_hexagon_A2_vadduhs>;
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def : T_PP_pat <A2_vaddw, int_hexagon_A2_vaddw>;
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def : T_PP_pat <A2_vaddws, int_hexagon_A2_vaddws>;
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// ALU64 - Vector average
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def : T_PP_pat <A2_vavgub, int_hexagon_A2_vavgub>;
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def : T_PP_pat <A2_vavgubr, int_hexagon_A2_vavgubr>;
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def : T_PP_pat <A2_vavgh, int_hexagon_A2_vavgh>;
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def : T_PP_pat <A2_vavghr, int_hexagon_A2_vavghr>;
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def : T_PP_pat <A2_vavghcr, int_hexagon_A2_vavghcr>;
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def : T_PP_pat <A2_vavguh, int_hexagon_A2_vavguh>;
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def : T_PP_pat <A2_vavguhr, int_hexagon_A2_vavguhr>;
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def : T_PP_pat <A2_vavgw, int_hexagon_A2_vavgw>;
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def : T_PP_pat <A2_vavgwr, int_hexagon_A2_vavgwr>;
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def : T_PP_pat <A2_vavgwcr, int_hexagon_A2_vavgwcr>;
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def : T_PP_pat <A2_vavguw, int_hexagon_A2_vavguw>;
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def : T_PP_pat <A2_vavguwr, int_hexagon_A2_vavguwr>;
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// ALU64 - Vector negative average
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def : T_PP_pat <A2_vnavgh, int_hexagon_A2_vnavgh>;
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def : T_PP_pat <A2_vnavghr, int_hexagon_A2_vnavghr>;
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def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>;
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def : T_PP_pat <A2_vnavgw, int_hexagon_A2_vnavgw>;
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def : T_PP_pat <A2_vnavgwr, int_hexagon_A2_vnavgwr>;
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def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>;
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// ALU64 - Vector max
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def : T_PP_pat <A2_vmaxh, int_hexagon_A2_vmaxh>;
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def : T_PP_pat <A2_vmaxw, int_hexagon_A2_vmaxw>;
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def : T_PP_pat <A2_vmaxub, int_hexagon_A2_vmaxub>;
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def : T_PP_pat <A2_vmaxuh, int_hexagon_A2_vmaxuh>;
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def : T_PP_pat <A2_vmaxuw, int_hexagon_A2_vmaxuw>;
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// ALU64 - Vector min
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def : T_PP_pat <A2_vminh, int_hexagon_A2_vminh>;
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def : T_PP_pat <A2_vminw, int_hexagon_A2_vminw>;
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def : T_PP_pat <A2_vminub, int_hexagon_A2_vminub>;
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def : T_PP_pat <A2_vminuh, int_hexagon_A2_vminuh>;
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def : T_PP_pat <A2_vminuw, int_hexagon_A2_vminuw>;
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// ALU64 - Vector sub
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def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubub>;
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def : T_PP_pat <A2_vsububs, int_hexagon_A2_vsububs>;
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def : T_PP_pat <A2_vsubh, int_hexagon_A2_vsubh>;
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def : T_PP_pat <A2_vsubhs, int_hexagon_A2_vsubhs>;
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def : T_PP_pat <A2_vsubuhs, int_hexagon_A2_vsubuhs>;
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def : T_PP_pat <A2_vsubw, int_hexagon_A2_vsubw>;
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def : T_PP_pat <A2_vsubws, int_hexagon_A2_vsubws>;
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// ALU64 - Vector compare bytes
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def : T_PP_pat <A2_vcmpbeq, int_hexagon_A2_vcmpbeq>;
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def : T_PP_pat <A4_vcmpbgt, int_hexagon_A4_vcmpbgt>;
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def : T_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>;
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// ALU64 - Vector compare halfwords
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def : T_PP_pat <A2_vcmpheq, int_hexagon_A2_vcmpheq>;
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def : T_PP_pat <A2_vcmphgt, int_hexagon_A2_vcmphgt>;
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def : T_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>;
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// ALU64 - Vector compare words
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def : T_PP_pat <A2_vcmpweq, int_hexagon_A2_vcmpweq>;
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def : T_PP_pat <A2_vcmpwgt, int_hexagon_A2_vcmpwgt>;
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def : T_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>;
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// ALU64 / VB / Vector mux.
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def : Pat<(int_hexagon_C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
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(C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt)>;
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// MPY - Multiply and use full result
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// Rdd = mpy[u](Rs, Rt)
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def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>;
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@ -1387,60 +1480,6 @@ class di_LDInstPI_diu4<string opc, Intrinsic IntID>
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[],
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"$src1 = $dst">;
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/********************************************************************
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* ALU32/VH *
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*********************************************************************/
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// ALU32 / VH / Vector add halfwords.
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// Rd32=vadd[u]h(Rs32,Rt32:sat]
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def HEXAGON_A2_svaddh:
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si_ALU32_sisi <"vaddh", int_hexagon_A2_svaddh>;
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def HEXAGON_A2_svaddhs:
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si_ALU32_sisi_sat <"vaddh", int_hexagon_A2_svaddhs>;
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def HEXAGON_A2_svadduhs:
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si_ALU32_sisi_sat <"vadduh", int_hexagon_A2_svadduhs>;
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// ALU32 / VH / Vector average halfwords.
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def HEXAGON_A2_svavgh:
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si_ALU32_sisi <"vavgh", int_hexagon_A2_svavgh>;
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def HEXAGON_A2_svavghs:
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si_ALU32_sisi_rnd <"vavgh", int_hexagon_A2_svavghs>;
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def HEXAGON_A2_svnavgh:
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si_ALU32_sisi <"vnavgh", int_hexagon_A2_svnavgh>;
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// ALU32 / VH / Vector subtract halfwords.
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def HEXAGON_A2_svsubh:
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si_ALU32_sisi <"vsubh", int_hexagon_A2_svsubh>;
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def HEXAGON_A2_svsubhs:
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si_ALU32_sisi_sat <"vsubh", int_hexagon_A2_svsubhs>;
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def HEXAGON_A2_svsubuhs:
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si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>;
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// ALU64 / ALU / Transfer register.
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def HEXAGON_A2_tfrp:
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di_ALU64_di <"", int_hexagon_A2_tfrp>;
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/********************************************************************
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* ALU64/VB *
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*********************************************************************/
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// ALU64 / VB / Vector add unsigned bytes.
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def HEXAGON_A2_vaddub:
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di_ALU64_didi <"vaddub", int_hexagon_A2_vaddub>;
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def HEXAGON_A2_vaddubs:
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di_ALU64_didi_sat <"vaddub", int_hexagon_A2_vaddubs>;
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// ALU64 / VB / Vector average unsigned bytes.
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def HEXAGON_A2_vavgub:
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di_ALU64_didi <"vavgub", int_hexagon_A2_vavgub>;
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def HEXAGON_A2_vavgubr:
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di_ALU64_didi_rnd <"vavgub", int_hexagon_A2_vavgubr>;
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// ALU64 / VB / Vector compare unsigned bytes.
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def HEXAGON_A2_vcmpbeq:
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qi_ALU64_didi <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
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def HEXAGON_A2_vcmpbgtu:
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qi_ALU64_didi <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
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// ALU64 / VB / Vector maximum/minimum unsigned bytes.
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def HEXAGON_A2_vmaxub:
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@ -1454,127 +1493,6 @@ def HEXAGON_A2_vsubub:
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def HEXAGON_A2_vsububs:
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di_ALU64_didi_sat <"vsubub", int_hexagon_A2_vsububs>;
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// ALU64 / VB / Vector mux.
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def HEXAGON_C2_vmux:
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di_ALU64_qididi <"vmux", int_hexagon_C2_vmux>;
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/********************************************************************
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* ALU64/VH *
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*********************************************************************/
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// ALU64 / VH / Vector add halfwords.
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// Rdd64=vadd[u]h(Rss64,Rtt64:sat]
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def HEXAGON_A2_vaddh:
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di_ALU64_didi <"vaddh", int_hexagon_A2_vaddh>;
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def HEXAGON_A2_vaddhs:
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di_ALU64_didi_sat <"vaddh", int_hexagon_A2_vaddhs>;
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def HEXAGON_A2_vadduhs:
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di_ALU64_didi_sat <"vadduh", int_hexagon_A2_vadduhs>;
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// ALU64 / VH / Vector average halfwords.
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// Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
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def HEXAGON_A2_vavgh:
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di_ALU64_didi <"vavgh", int_hexagon_A2_vavgh>;
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def HEXAGON_A2_vavghcr:
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di_ALU64_didi_crnd <"vavgh", int_hexagon_A2_vavghcr>;
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def HEXAGON_A2_vavghr:
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di_ALU64_didi_rnd <"vavgh", int_hexagon_A2_vavghr>;
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def HEXAGON_A2_vavguh:
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di_ALU64_didi <"vavguh", int_hexagon_A2_vavguh>;
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def HEXAGON_A2_vavguhr:
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di_ALU64_didi_rnd <"vavguh", int_hexagon_A2_vavguhr>;
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def HEXAGON_A2_vnavgh:
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di_ALU64_didi <"vnavgh", int_hexagon_A2_vnavgh>;
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def HEXAGON_A2_vnavghcr:
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di_ALU64_didi_crnd_sat <"vnavgh", int_hexagon_A2_vnavghcr>;
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def HEXAGON_A2_vnavghr:
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di_ALU64_didi_rnd_sat <"vnavgh", int_hexagon_A2_vnavghr>;
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// ALU64 / VH / Vector compare halfwords.
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def HEXAGON_A2_vcmpheq:
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qi_ALU64_didi <"vcmph.eq", int_hexagon_A2_vcmpheq>;
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def HEXAGON_A2_vcmphgt:
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qi_ALU64_didi <"vcmph.gt", int_hexagon_A2_vcmphgt>;
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def HEXAGON_A2_vcmphgtu:
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qi_ALU64_didi <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
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// ALU64 / VH / Vector maximum halfwords.
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def HEXAGON_A2_vmaxh:
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di_ALU64_didi <"vmaxh", int_hexagon_A2_vmaxh>;
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def HEXAGON_A2_vmaxuh:
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di_ALU64_didi <"vmaxuh", int_hexagon_A2_vmaxuh>;
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// ALU64 / VH / Vector minimum halfwords.
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def HEXAGON_A2_vminh:
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di_ALU64_didi <"vminh", int_hexagon_A2_vminh>;
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def HEXAGON_A2_vminuh:
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di_ALU64_didi <"vminuh", int_hexagon_A2_vminuh>;
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// ALU64 / VH / Vector subtract halfwords.
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def HEXAGON_A2_vsubh:
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di_ALU64_didi <"vsubh", int_hexagon_A2_vsubh>;
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def HEXAGON_A2_vsubhs:
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di_ALU64_didi_sat <"vsubh", int_hexagon_A2_vsubhs>;
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def HEXAGON_A2_vsubuhs:
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di_ALU64_didi_sat <"vsubuh", int_hexagon_A2_vsubuhs>;
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/********************************************************************
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* ALU64/VW *
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*********************************************************************/
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// ALU64 / VW / Vector add words.
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// Rdd32=vaddw(Rss32,Rtt32)[:sat]
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def HEXAGON_A2_vaddw:
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di_ALU64_didi <"vaddw", int_hexagon_A2_vaddw>;
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def HEXAGON_A2_vaddws:
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di_ALU64_didi_sat <"vaddw", int_hexagon_A2_vaddws>;
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// ALU64 / VW / Vector average words.
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def HEXAGON_A2_vavguw:
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di_ALU64_didi <"vavguw", int_hexagon_A2_vavguw>;
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def HEXAGON_A2_vavguwr:
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di_ALU64_didi_rnd <"vavguw", int_hexagon_A2_vavguwr>;
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def HEXAGON_A2_vavgw:
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di_ALU64_didi <"vavgw", int_hexagon_A2_vavgw>;
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def HEXAGON_A2_vavgwcr:
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di_ALU64_didi_crnd <"vavgw", int_hexagon_A2_vavgwcr>;
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def HEXAGON_A2_vavgwr:
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di_ALU64_didi_rnd <"vavgw", int_hexagon_A2_vavgwr>;
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def HEXAGON_A2_vnavgw:
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di_ALU64_didi <"vnavgw", int_hexagon_A2_vnavgw>;
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def HEXAGON_A2_vnavgwcr:
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di_ALU64_didi_crnd_sat <"vnavgw", int_hexagon_A2_vnavgwcr>;
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def HEXAGON_A2_vnavgwr:
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di_ALU64_didi_rnd_sat <"vnavgw", int_hexagon_A2_vnavgwr>;
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// ALU64 / VW / Vector compare words.
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def HEXAGON_A2_vcmpweq:
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qi_ALU64_didi <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
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def HEXAGON_A2_vcmpwgt:
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qi_ALU64_didi <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
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def HEXAGON_A2_vcmpwgtu:
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qi_ALU64_didi <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
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// ALU64 / VW / Vector maximum words.
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def HEXAGON_A2_vmaxw:
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di_ALU64_didi <"vmaxw", int_hexagon_A2_vmaxw>;
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def HEXAGON_A2_vmaxuw:
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di_ALU64_didi <"vmaxuw", int_hexagon_A2_vmaxuw>;
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// ALU64 / VW / Vector minimum words.
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def HEXAGON_A2_vminw:
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di_ALU64_didi <"vminw", int_hexagon_A2_vminw>;
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def HEXAGON_A2_vminuw:
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di_ALU64_didi <"vminuw", int_hexagon_A2_vminuw>;
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// ALU64 / VW / Vector subtract words.
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def HEXAGON_A2_vsubw:
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di_ALU64_didi <"vsubw", int_hexagon_A2_vsubw>;
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def HEXAGON_A2_vsubws:
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di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>;
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/********************************************************************
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* MTYPE/ALU *
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*********************************************************************/
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@ -34,6 +34,10 @@ def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
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def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
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def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
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// Vector reduce add unsigned halfwords
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def : Pat <(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2),
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(M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>;
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def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
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def: T_P_pat <S2_ct0p, int_hexagon_S2_ct0p>;
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@ -82,12 +86,39 @@ def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;
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def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
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def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
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// Vector conditional negate
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// Rdd=vcnegh(Rss,Rt)
|
||||
def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>;
|
||||
|
||||
// Shift an immediate left by register amount
|
||||
def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
|
||||
|
||||
// Vector reduce maximum halfwords
|
||||
def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>;
|
||||
def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>;
|
||||
|
||||
// Vector reduce maximum words
|
||||
def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>;
|
||||
def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>;
|
||||
|
||||
// Vector reduce minimum halfwords
|
||||
def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>;
|
||||
def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>;
|
||||
|
||||
// Vector reduce minimum words
|
||||
def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>;
|
||||
def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>;
|
||||
|
||||
// Vector conditional negate
|
||||
def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>;
|
||||
|
||||
// Logical xor with xor accumulation
|
||||
def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
|
||||
|
||||
// ALU64 - Vector min/max byte
|
||||
def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>;
|
||||
def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>;
|
||||
|
||||
// Shift and add/sub/and/or
|
||||
def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
|
||||
def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
|
||||
|
|
|
|||
|
|
@ -127,6 +127,72 @@ define i32 @A2_tfr(i32 %a) {
|
|||
}
|
||||
; CHECK: r0 = r0
|
||||
|
||||
; Vector add halfwords
|
||||
declare i32 @llvm.hexagon.A2.svaddh(i32, i32)
|
||||
define i32 @A2_svaddh(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.A2.svaddh(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vaddh(r0, r1)
|
||||
|
||||
declare i32 @llvm.hexagon.A2.svaddhs(i32, i32)
|
||||
define i32 @A2_svaddhs(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.A2.svaddhs(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vaddh(r0, r1):sat
|
||||
|
||||
declare i32 @llvm.hexagon.A2.svadduhs(i32, i32)
|
||||
define i32 @A2_svadduhs(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.A2.svadduhs(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vadduh(r0, r1):sat
|
||||
|
||||
; Vector average halfwords
|
||||
declare i32 @llvm.hexagon.A2.svavgh(i32, i32)
|
||||
define i32 @A2_svavgh(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.A2.svavgh(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vavgh(r0, r1)
|
||||
|
||||
declare i32 @llvm.hexagon.A2.svavghs(i32, i32)
|
||||
define i32 @A2_svavghs(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.A2.svavghs(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vavgh(r0, r1):rnd
|
||||
|
||||
declare i32 @llvm.hexagon.A2.svnavgh(i32, i32)
|
||||
define i32 @A2_svnavgh(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.A2.svnavgh(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vnavgh(r0, r1)
|
||||
|
||||
; Vector subtract halfwords
|
||||
declare i32 @llvm.hexagon.A2.svsubh(i32, i32)
|
||||
define i32 @A2_svsubh(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.A2.svsubh(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vsubh(r0, r1)
|
||||
|
||||
declare i32 @llvm.hexagon.A2.svsubhs(i32, i32)
|
||||
define i32 @A2_svsubhs(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.A2.svsubhs(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vsubh(r0, r1):sat
|
||||
|
||||
declare i32 @llvm.hexagon.A2.svsubuhs(i32, i32)
|
||||
define i32 @A2_svsubuhs(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.A2.svsubuhs(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vsubuh(r0, r1):sat
|
||||
|
||||
; Zero extend
|
||||
declare i32 @llvm.hexagon.A2.zxth(i32)
|
||||
define i32 @A2_zxth(i32 %a) {
|
||||
|
|
|
|||
|
|
@ -551,3 +551,470 @@ define i64 @A2_sxtw(i32 %a) {
|
|||
ret i64 %z
|
||||
}
|
||||
; CHECK: = sxtw(r0)
|
||||
|
||||
; Vector absolute value halfwords
|
||||
declare i64 @llvm.hexagon.A2.vabsh(i64)
|
||||
define i64 @A2_vabsh(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.A2.vabsh(i64 %a)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vabsh(r1:0)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vabshsat(i64)
|
||||
define i64 @A2_vabshsat(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.A2.vabshsat(i64 %a)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vabsh(r1:0):sat
|
||||
|
||||
; Vector absolute value words
|
||||
declare i64 @llvm.hexagon.A2.vabsw(i64)
|
||||
define i64 @A2_vabsw(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.A2.vabsw(i64 %a)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vabsw(r1:0)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vabswsat(i64)
|
||||
define i64 @A2_vabswsat(i64 %a) {
|
||||
%z = call i64 @llvm.hexagon.A2.vabswsat(i64 %a)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vabsw(r1:0):sat
|
||||
|
||||
; Vector absolute difference halfwords
|
||||
declare i64 @llvm.hexagon.M2.vabsdiffh(i64, i64)
|
||||
define i64 @M2_vabsdiffh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.M2.vabsdiffh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vabsdiffh(r1:0, r3:2)
|
||||
|
||||
; Vector absolute difference words
|
||||
declare i64 @llvm.hexagon.M2.vabsdiffw(i64, i64)
|
||||
define i64 @M2_vabsdiffw(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.M2.vabsdiffw(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vabsdiffw(r1:0, r3:2)
|
||||
|
||||
; Vector add halfwords
|
||||
declare i64 @llvm.hexagon.A2.vaddh(i64, i64)
|
||||
define i64 @A2_vaddh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vaddh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vaddh(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vaddhs(i64, i64)
|
||||
define i64 @A2_vaddhs(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vaddhs(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vaddh(r1:0, r3:2):sat
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vadduhs(i64, i64)
|
||||
define i64 @A2_vadduhs(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vadduhs(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vadduh(r1:0, r3:2):sat
|
||||
|
||||
; Vector add halfwords with saturate and pack to unsigned bytes
|
||||
declare i32 @llvm.hexagon.A5.vaddhubs(i64, i64)
|
||||
define i32 @A5_vaddhubs(i64 %a, i64 %b) {
|
||||
%z = call i32 @llvm.hexagon.A5.vaddhubs(i64 %a, i64 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vaddhub(r1:0, r3:2):sat
|
||||
|
||||
; Vector reduce add unsigned bytes
|
||||
declare i64 @llvm.hexagon.A2.vraddub(i64, i64)
|
||||
define i64 @A2_vraddub(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vraddub(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vraddub(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vraddub.acc(i64, i64, i64)
|
||||
define i64 @A2_vraddub_acc(i64 %a, i64 %b, i64 %c) {
|
||||
%z = call i64 @llvm.hexagon.A2.vraddub.acc(i64 %a, i64 %b, i64 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 += vraddub(r3:2, r5:4)
|
||||
|
||||
; Vector reduce add halfwords
|
||||
declare i32 @llvm.hexagon.M2.vradduh(i64, i64)
|
||||
define i32 @M2_vradduh(i64 %a, i64 %b) {
|
||||
%z = call i32 @llvm.hexagon.M2.vradduh(i64 %a, i64 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vradduh(r1:0, r3:2)
|
||||
|
||||
declare i32 @llvm.hexagon.M2.vraddh(i64, i64)
|
||||
define i32 @M2_vraddh(i64 %a, i64 %b) {
|
||||
%z = call i32 @llvm.hexagon.M2.vraddh(i64 %a, i64 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vraddh(r1:0, r3:2)
|
||||
|
||||
; Vector add bytes
|
||||
declare i64 @llvm.hexagon.A2.vaddub(i64, i64)
|
||||
define i64 @A2_vaddub(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vaddub(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vaddub(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vaddubs(i64, i64)
|
||||
define i64 @A2_vaddubs(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vaddubs(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vaddub(r1:0, r3:2):sat
|
||||
|
||||
; Vector add words
|
||||
declare i64 @llvm.hexagon.A2.vaddw(i64, i64)
|
||||
define i64 @A2_vaddw(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vaddw(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vaddw(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vaddws(i64, i64)
|
||||
define i64 @A2_vaddws(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vaddws(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vaddw(r1:0, r3:2):sat
|
||||
|
||||
; Vector average halfwords
|
||||
declare i64 @llvm.hexagon.A2.vavgh(i64, i64)
|
||||
define i64 @A2_vavgh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavgh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavgh(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vavghr(i64, i64)
|
||||
define i64 @A2_vavghr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavghr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavgh(r1:0, r3:2):rnd
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vavghcr(i64, i64)
|
||||
define i64 @A2_vavghcr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavghcr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavgh(r1:0, r3:2):crnd
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vavguh(i64, i64)
|
||||
define i64 @A2_vavguh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavguh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavguh(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vavguhr(i64, i64)
|
||||
define i64 @A2_vavguhr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavguhr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavguh(r1:0, r3:2):rnd
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vnavgh(i64, i64)
|
||||
define i64 @A2_vnavgh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vnavgh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vnavgh(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vnavghr(i64, i64)
|
||||
define i64 @A2_vnavghr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vnavghr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vnavgh(r1:0, r3:2):rnd
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vnavghcr(i64, i64)
|
||||
define i64 @A2_vnavghcr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vnavghcr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vnavgh(r1:0, r3:2):crnd
|
||||
|
||||
; Vector average unsigned bytes
|
||||
declare i64 @llvm.hexagon.A2.vavgub(i64, i64)
|
||||
define i64 @A2_vavgub(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavgub(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavgub(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vavgubr(i64, i64)
|
||||
define i64 @A2_vavgubr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavgubr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavgub(r1:0, r3:2):rnd
|
||||
|
||||
; Vector average words
|
||||
declare i64 @llvm.hexagon.A2.vavgw(i64, i64)
|
||||
define i64 @A2_vavgw(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavgw(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavgw(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vavgwr(i64, i64)
|
||||
define i64 @A2_vavgwr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavgwr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavgw(r1:0, r3:2):rnd
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vavgwcr(i64, i64)
|
||||
define i64 @A2_vavgwcr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavgwcr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavgw(r1:0, r3:2):crnd
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vavguw(i64, i64)
|
||||
define i64 @A2_vavguw(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavguw(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavguw(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vavguwr(i64, i64)
|
||||
define i64 @A2_vavguwr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vavguwr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vavguw(r1:0, r3:2):rnd
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vnavgw(i64, i64)
|
||||
define i64 @A2_vnavgw(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vnavgw(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vnavgw(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vnavgwr(i64, i64)
|
||||
define i64 @A2_vnavgwr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vnavgwr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vnavgw(r1:0, r3:2):rnd
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vnavgwcr(i64, i64)
|
||||
define i64 @A2_vnavgwcr(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vnavgwcr(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vnavgw(r1:0, r3:2):crnd
|
||||
|
||||
; Vector conditional negate
|
||||
declare i64 @llvm.hexagon.S2.vcnegh(i64, i32)
|
||||
define i64 @S2_vcnegh(i64 %a, i32 %b) {
|
||||
%z = call i64 @llvm.hexagon.S2.vcnegh(i64 %a, i32 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vcnegh(r1:0, r2)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.vrcnegh(i64, i64, i32)
|
||||
define i64 @S2_vrcnegh(i64 %a, i64 %b, i32 %c) {
|
||||
%z = call i64 @llvm.hexagon.S2.vrcnegh(i64 %a, i64 %b, i32 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 += vrcnegh(r3:2, r4)
|
||||
|
||||
; Vector maximum bytes
|
||||
declare i64 @llvm.hexagon.A2.vmaxub(i64, i64)
|
||||
define i64 @A2_vmaxub(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vmaxub(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vmaxub(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vmaxb(i64, i64)
|
||||
define i64 @A2_vmaxb(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vmaxb(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vmaxb(r1:0, r3:2)
|
||||
|
||||
; Vector maximum halfwords
|
||||
declare i64 @llvm.hexagon.A2.vmaxh(i64, i64)
|
||||
define i64 @A2_vmaxh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vmaxh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vmaxh(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vmaxuh(i64, i64)
|
||||
define i64 @A2_vmaxuh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vmaxuh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vmaxuh(r1:0, r3:2)
|
||||
|
||||
; Vector reduce maximum halfwords
|
||||
declare i64 @llvm.hexagon.A4.vrmaxh(i64, i64, i32)
|
||||
define i64 @A4_vrmaxh(i64 %a, i64 %b, i32 %c) {
|
||||
%z = call i64 @llvm.hexagon.A4.vrmaxh(i64 %a, i64 %b, i32 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vrmaxh(r3:2, r4)
|
||||
|
||||
declare i64 @llvm.hexagon.A4.vrmaxuh(i64, i64, i32)
|
||||
define i64 @A4_vrmaxuh(i64 %a, i64 %b, i32 %c) {
|
||||
%z = call i64 @llvm.hexagon.A4.vrmaxuh(i64 %a, i64 %b, i32 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vrmaxuh(r3:2, r4)
|
||||
|
||||
; Vector reduce maximum words
|
||||
declare i64 @llvm.hexagon.A4.vrmaxw(i64, i64, i32)
|
||||
define i64 @A4_vrmaxw(i64 %a, i64 %b, i32 %c) {
|
||||
%z = call i64 @llvm.hexagon.A4.vrmaxw(i64 %a, i64 %b, i32 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vrmaxw(r3:2, r4)
|
||||
|
||||
declare i64 @llvm.hexagon.A4.vrmaxuw(i64, i64, i32)
|
||||
define i64 @A4_vrmaxuw(i64 %a, i64 %b, i32 %c) {
|
||||
%z = call i64 @llvm.hexagon.A4.vrmaxuw(i64 %a, i64 %b, i32 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vrmaxuw(r3:2, r4)
|
||||
|
||||
; Vector minimum bytes
|
||||
declare i64 @llvm.hexagon.A2.vminub(i64, i64)
|
||||
define i64 @A2_vminub(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vminub(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vminub(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vminb(i64, i64)
|
||||
define i64 @A2_vminb(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vminb(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vminb(r1:0, r3:2)
|
||||
|
||||
; Vector minimum halfwords
|
||||
declare i64 @llvm.hexagon.A2.vminh(i64, i64)
|
||||
define i64 @A2_vminh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vminh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vminh(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vminuh(i64, i64)
|
||||
define i64 @A2_vminuh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vminuh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vminuh(r1:0, r3:2)
|
||||
|
||||
; Vector reduce minimum halfwords
|
||||
declare i64 @llvm.hexagon.A4.vrminh(i64, i64, i32)
|
||||
define i64 @A4_vrminh(i64 %a, i64 %b, i32 %c) {
|
||||
%z = call i64 @llvm.hexagon.A4.vrminh(i64 %a, i64 %b, i32 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vrminh(r3:2, r4)
|
||||
|
||||
declare i64 @llvm.hexagon.A4.vrminuh(i64, i64, i32)
|
||||
define i64 @A4_vrminuh(i64 %a, i64 %b, i32 %c) {
|
||||
%z = call i64 @llvm.hexagon.A4.vrminuh(i64 %a, i64 %b, i32 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vrminuh(r3:2, r4)
|
||||
|
||||
; Vector reduce minimum words
|
||||
declare i64 @llvm.hexagon.A4.vrminw(i64, i64, i32)
|
||||
define i64 @A4_vrminw(i64 %a, i64 %b, i32 %c) {
|
||||
%z = call i64 @llvm.hexagon.A4.vrminw(i64 %a, i64 %b, i32 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vrminw(r3:2, r4)
|
||||
|
||||
declare i64 @llvm.hexagon.A4.vrminuw(i64, i64, i32)
|
||||
define i64 @A4_vrminuw(i64 %a, i64 %b, i32 %c) {
|
||||
%z = call i64 @llvm.hexagon.A4.vrminuw(i64 %a, i64 %b, i32 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vrminuw(r3:2, r4)
|
||||
|
||||
; Vector sum of absolute differences unsigned bytes
|
||||
declare i64 @llvm.hexagon.A2.vrsadub(i64, i64)
|
||||
define i64 @A2_vrsadub(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vrsadub(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vrsadub(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vrsadub.acc(i64, i64, i64)
|
||||
define i64 @A2_vrsadub_acc(i64 %a, i64 %b, i64 %c) {
|
||||
%z = call i64 @llvm.hexagon.A2.vrsadub.acc(i64 %a, i64 %b, i64 %c)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 += vrsadub(r3:2, r5:4)
|
||||
|
||||
; Vector subtract halfwords
|
||||
declare i64 @llvm.hexagon.A2.vsubh(i64, i64)
|
||||
define i64 @A2_vsubh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vsubh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vsubh(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vsubhs(i64, i64)
|
||||
define i64 @A2_vsubhs(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vsubhs(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vsubh(r1:0, r3:2):sat
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vsubuhs(i64, i64)
|
||||
define i64 @A2_vsubuhs(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vsubuhs(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vsubuh(r1:0, r3:2):sat
|
||||
|
||||
; Vector subtract bytes
|
||||
declare i64 @llvm.hexagon.A2.vsubub(i64, i64)
|
||||
define i64 @A2_vsubub(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vsubub(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vsubub(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vsububs(i64, i64)
|
||||
define i64 @A2_vsububs(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vsububs(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vsubub(r1:0, r3:2):sat
|
||||
|
||||
; Vector subtract words
|
||||
declare i64 @llvm.hexagon.A2.vsubw(i64, i64)
|
||||
define i64 @A2_vsubw(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vsubw(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vsubw(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.vsubws(i64, i64)
|
||||
define i64 @A2_vsubws(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.A2.vsubws(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vsubw(r1:0, r3:2):sat
|
||||
|
|
|
|||
Loading…
Reference in New Issue