forked from OSchip/llvm-project
Update syntax for amx.tile_muli to use two Unit attr to mark the zext case
This makes the annotation tied to the operand and the use of a keyword more explicit/readable on what it means. Differential Revision: https://reviews.llvm.org/D99001
This commit is contained in:
Mehdi Amini
parent
ea48bf8649
commit
cdb6eb7e83
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@ -196,14 +196,14 @@ def TileMulIOp : AMX_Op<"tile_muli", [NoSideEffect, AllTypesMatch<["acc", "res"]
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into a "m x n" destination tile. Supports all "si32 <- s/ui8 x s/ui8"
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combinations (4 bytes packed into dwords in the columns of both the
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source operand tiles; the zero or sign extension is specified with
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the attributes). The operation is eventually lowered into one of
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the "tdpbssd", "tdpbsud", "tdpbusd", or "tdpbuud" instructions with
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the corresponding tile configuration.
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the attributes and default to sign extended). The operation is eventually
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lowered into one of the "tdpbssd", "tdpbsud", "tdpbusd", or "tdpbuud"
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instructions with the corresponding tile configuration.
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Example:
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```mlir
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%0 = amx.tile_muli %a, %b, %c [true, true]
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%0 = amx.tile_muli %a zext, %b zext, %c
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: vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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```
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}];
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@ -211,7 +211,9 @@ def TileMulIOp : AMX_Op<"tile_muli", [NoSideEffect, AllTypesMatch<["acc", "res"]
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let arguments = (ins VectorOfRankAndType<[2], [I32, I8]>:$lhs,
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VectorOfRankAndType<[2], [I32, I8]>:$rhs,
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VectorOfRankAndType<[2], [I32, I8]>:$acc,
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BoolArrayAttr:$zext);
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UnitAttr:$isZextLhs,
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UnitAttr:$isZextRhs
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);
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let results = (outs VectorOfRankAndType<[2], [I32, I8]>:$res);
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let extraClassDeclaration = [{
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VectorType getLhsVectorType() {
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@ -224,7 +226,7 @@ def TileMulIOp : AMX_Op<"tile_muli", [NoSideEffect, AllTypesMatch<["acc", "res"]
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return res().getType().cast<VectorType>();
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}
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}];
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let assemblyFormat = "$lhs `,` $rhs `,` $acc $zext attr-dict `:` "
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let assemblyFormat = "$lhs (`zext` $isZextLhs^)? `,` $rhs (`zext` $isZextRhs^)? `,` $acc attr-dict `:` "
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"type($lhs) `,` type($rhs) `,` type($acc) ";
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}
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@ -85,8 +85,6 @@ static LogicalResult verify(amx::TileMulFOp op) {
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}
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static LogicalResult verify(amx::TileMulIOp op) {
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if (op.zext().size() != 2)
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return op.emitOpError("unexpected zext length");
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VectorType aType = op.getLhsVectorType();
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VectorType bType = op.getRhsVectorType();
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VectorType cType = op.getVectorType();
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@ -191,8 +191,8 @@ struct TileMulIConversion : public ConvertOpToLLVMPattern<TileMulIOp> {
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getTileSizes(rewriter, *getTypeConverter(), bType, op.getLoc());
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// Replace operation with intrinsic.
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Type resType = typeConverter->convertType(cType);
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bool zexta = op.zext()[0].cast<BoolAttr>().getValue();
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bool zextb = op.zext()[1].cast<BoolAttr>().getValue();
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bool zexta = op.isZextLhs();
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bool zextb = op.isZextRhs();
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if (zexta && zextb)
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rewriter.replaceOpWithNewOp<amx::x86_amx_tdpbuud>(
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op, resType, tsza.first, tszb.second, tsza.second, adaptor.acc(),
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@ -46,13 +46,3 @@ func @multsize() {
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// expected-error@+1 {{'amx.tile_mulf' op bad mult shape: 4 x 4 x 4}}
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%3 = amx.tile_mulf %0, %1, %2 : vector<8x8xbf16>, vector<8x8xbf16>, vector<4x4xf32>
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}
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// -----
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func @zextsize() {
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%0 = amx.tile_zero : vector<8x8xi8>
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%1 = amx.tile_zero : vector<8x8xi8>
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%2 = amx.tile_zero : vector<8x8xi32>
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// expected-error@+1 {{'amx.tile_muli' op unexpected zext length}}
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%3 = amx.tile_muli %0, %1, %2 [true] : vector<8x8xi8>, vector<8x8xi8>, vector<8x8xi32>
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}
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@ -17,13 +17,13 @@ func @muli(%arg0: memref<?x?xi8>, %arg1: memref<?x?xi32>) {
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%1 = amx.tile_zero : vector<16x64xi8>
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%2 = amx.tile_load %arg0[%0, %0] : memref<?x?xi8> into vector<16x64xi8>
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%3 = amx.tile_load %arg1[%0, %0] : memref<?x?xi32> into vector<16x16xi32>
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%4 = amx.tile_muli %1, %2, %3 [true, true] : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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%4 = amx.tile_muli %1 zext, %2 zext, %3 : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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amx.tile_store %arg1[%0, %0], %4 : memref<?x?xi32>, vector<16x16xi32>
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%5 = amx.tile_muli %1, %2, %3 [false, false] : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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%5 = amx.tile_muli %1, %2, %3 : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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amx.tile_store %arg1[%0, %0], %5 : memref<?x?xi32>, vector<16x16xi32>
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%6 = amx.tile_muli %1, %2, %3 [true, false] : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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%6 = amx.tile_muli %1 zext, %2, %3 : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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amx.tile_store %arg1[%0, %0], %6 : memref<?x?xi32>, vector<16x16xi32>
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%7 = amx.tile_muli %1, %2, %3 [false, true] : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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%7 = amx.tile_muli %1, %2 zext, %3 : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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amx.tile_store %arg1[%0, %0], %7 : memref<?x?xi32>, vector<16x16xi32>
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return
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}
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@ -28,14 +28,22 @@ func @tmulf(%arg0: memref<?x?xbf16>, %arg1: memref<?x?xf32>) {
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// CHECK: %[[x:.*]] = amx.tile_load %{{.*}}[%{{.*}}, %{{.*}}] : memref<?x?xi8> into vector<16x64xi8>
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// CHECK: %[[y:.*]] = amx.tile_load %{{.*}}[%{{.*}}, %{{.*}}] : memref<?x?xi8> into vector<16x64xi8>
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// CHECK: %[[z:.*]] = amx.tile_load %{{.*}}[%{{.*}}, %{{.*}}] : memref<?x?xi32> into vector<16x16xi32>
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// CHECK: %[[m:.*]] = amx.tile_muli %[[x]], %[[y]], %[[z]] [true, true] : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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// CHECK: %[[m:.*]] = amx.tile_muli %[[x]] zext, %[[y]] zext, %[[z]] : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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// CHECK: amx.tile_store %{{.*}}[%{{.*}}, %{{.*}}], %[[m]] : memref<?x?xi32>, vector<16x16xi32>
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// Verify the parsing/printing of the sign-extension annotation.
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// CHECK: amx.tile_muli %{{.*}}, %{{.*}} zext, %{{.*}}
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// CHECK: amx.tile_muli %{{.*}} zext, %{{.*}}, %{{.*}}
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// CHECK: amx.tile_muli %{{.*}}, %{{.*}}, %{{.*}}
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func @tmuli(%arg0: memref<?x?xi8>, %arg1: memref<?x?xi8>, %arg2: memref<?x?xi32>) {
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%0 = constant 0 : index
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%1 = amx.tile_load %arg0[%0, %0] : memref<?x?xi8> into vector<16x64xi8>
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%2 = amx.tile_load %arg1[%0, %0] : memref<?x?xi8> into vector<16x64xi8>
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%3 = amx.tile_load %arg2[%0, %0] : memref<?x?xi32> into vector<16x16xi32>
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%4 = amx.tile_muli %1, %2, %3 [true, true] : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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%4 = amx.tile_muli %1 zext, %2 zext, %3 : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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amx.tile_store %arg2[%0, %0], %4 : memref<?x?xi32>, vector<16x16xi32>
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// Verify the various `zext` combinations.
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%5 = amx.tile_muli %1, %2 zext, %3 : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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%6 = amx.tile_muli %1 zext, %2, %3 : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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%7 = amx.tile_muli %1, %2, %3 : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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return
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}
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@ -24,7 +24,7 @@ func @kernel1(%arg0: memref<16x16xi8>,
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%1 = amx.tile_load %arg0[%0, %0] : memref<16x16xi8> into vector<16x16xi8>
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%2 = amx.tile_load %arg1[%0, %0] : memref<4x16xi8> into vector<4x16xi8>
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%3 = amx.tile_zero : vector<16x4xi32>
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%4 = amx.tile_muli %1, %2, %3 [false, false] : vector<16x16xi8>, vector<4x16xi8>, vector<16x4xi32>
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%4 = amx.tile_muli %1, %2, %3 : vector<16x16xi8>, vector<4x16xi8>, vector<16x4xi32>
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amx.tile_store %arg2[%0, %0], %4 : memref<16x4xi32>, vector<16x4xi32>
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return
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}
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@ -36,7 +36,7 @@ func @kernel2(%arg0: memref<16x16xi8>,
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%1 = amx.tile_load %arg0[%0, %0] : memref<16x16xi8> into vector<16x16xi8>
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%2 = amx.tile_load %arg1[%0, %0] : memref<4x16xi8> into vector<4x16xi8>
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%3 = amx.tile_zero : vector<16x4xi32>
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%4 = amx.tile_muli %1, %2, %3 [false, true] : vector<16x16xi8>, vector<4x16xi8>, vector<16x4xi32>
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%4 = amx.tile_muli %1, %2 zext, %3 : vector<16x16xi8>, vector<4x16xi8>, vector<16x4xi32>
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amx.tile_store %arg2[%0, %0], %4 : memref<16x4xi32>, vector<16x4xi32>
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return
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}
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@ -48,7 +48,7 @@ func @kernel3(%arg0: memref<16x16xi8>,
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%1 = amx.tile_load %arg0[%0, %0] : memref<16x16xi8> into vector<16x16xi8>
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%2 = amx.tile_load %arg1[%0, %0] : memref<4x16xi8> into vector<4x16xi8>
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%3 = amx.tile_zero : vector<16x4xi32>
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%4 = amx.tile_muli %1, %2, %3 [true, false] : vector<16x16xi8>, vector<4x16xi8>, vector<16x4xi32>
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%4 = amx.tile_muli %1 zext, %2, %3 : vector<16x16xi8>, vector<4x16xi8>, vector<16x4xi32>
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amx.tile_store %arg2[%0, %0], %4 : memref<16x4xi32>, vector<16x4xi32>
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return
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}
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@ -60,7 +60,7 @@ func @kernel4(%arg0: memref<16x16xi8>,
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%1 = amx.tile_load %arg0[%0, %0] : memref<16x16xi8> into vector<16x16xi8>
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%2 = amx.tile_load %arg1[%0, %0] : memref<4x16xi8> into vector<4x16xi8>
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%3 = amx.tile_zero : vector<16x4xi32>
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%4 = amx.tile_muli %1, %2, %3 [true, true] : vector<16x16xi8>, vector<4x16xi8>, vector<16x4xi32>
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%4 = amx.tile_muli %1 zext, %2 zext, %3 : vector<16x16xi8>, vector<4x16xi8>, vector<16x4xi32>
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amx.tile_store %arg2[%0, %0], %4 : memref<16x4xi32>, vector<16x4xi32>
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return
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}
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@ -13,7 +13,7 @@ func @kernel1(%arg0: memref<2x8xi8>,
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%1 = amx.tile_load %arg0[%0, %0] : memref<2x8xi8> into vector<2x8xi8>
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%2 = amx.tile_load %arg1[%0, %0] : memref<2x8xi8> into vector<2x8xi8>
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%3 = amx.tile_zero : vector<2x2xi32>
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%4 = amx.tile_muli %1, %2, %3 [true, true] : vector<2x8xi8>, vector<2x8xi8>, vector<2x2xi32>
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%4 = amx.tile_muli %1 zext, %2 zext, %3 : vector<2x8xi8>, vector<2x8xi8>, vector<2x2xi32>
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amx.tile_store %arg2[%0, %0], %4 : memref<2x2xi32>, vector<2x2xi32>
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return
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}
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@ -26,7 +26,7 @@ func @kernel2(%arg0: memref<2x8xi8>,
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%1 = amx.tile_load %arg0[%0, %0] : memref<2x8xi8> into vector<2x8xi8>
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%2 = amx.tile_load %arg1[%0, %0] : memref<2x8xi8> into vector<2x8xi8>
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%3 = amx.tile_load %arg2[%0, %0] : memref<2x2xi32> into vector<2x2xi32>
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%4 = amx.tile_muli %1, %2, %3 [true, true] : vector<2x8xi8>, vector<2x8xi8>, vector<2x2xi32>
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%4 = amx.tile_muli %1 zext, %2 zext, %3 : vector<2x8xi8>, vector<2x8xi8>, vector<2x2xi32>
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amx.tile_store %arg2[%0, %0], %4 : memref<2x2xi32>, vector<2x2xi32>
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return
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}
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