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[X86] Add -x86-experimental-vector-widening-legalization check to combineSelect and combineSetCC to cover vXi16/vXi8 promotion without BWI. 

I don't yet have any test cases for this, but its the right thing to do based on log file inspection.

llvm-svn: 347151
This commit is contained in:
Craig Topper 2018-11-18 08:30:09 +00:00
parent b03f80a21c
commit cd94a7c227
1 changed files with 5 additions and 2 deletions
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7
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -33650,7 +33650,8 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// Since SKX these selects have a proper lowering.
if (Subtarget.hasAVX512() && !Subtarget.hasBWI() && CondVT.isVector() &&
CondVT.getVectorElementType() == MVT::i1 &&
VT.getVectorNumElements() > 4 &&
(ExperimentalVectorWideningLegalization ||
VT.getVectorNumElements() > 4) &&
(VT.getVectorElementType() == MVT::i8 ||
VT.getVectorElementType() == MVT::i16)) {
Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
@ -39186,7 +39187,9 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG,
// NOTE: The element count check is to ignore operand types that need to
// go through type promotion to a 128-bit vector.
if (Subtarget.hasAVX512() && !Subtarget.hasBWI() && VT.isVector() &&
VT.getVectorElementType() == MVT::i1 && VT.getVectorNumElements() > 4 &&
VT.getVectorElementType() == MVT::i1 &&
(ExperimentalVectorWideningLegalization ||
VT.getVectorNumElements() > 4) &&
(OpVT.getVectorElementType() == MVT::i8 ||
OpVT.getVectorElementType() == MVT::i16)) {
SDValue Setcc = DAG.getNode(ISD::SETCC, DL, OpVT, LHS, RHS,