forked from OSchip/llvm-project
[InstCombine] Add additional tests for converting to sadd.sat with sign bits. NFC
This commit is contained in:
David Green
parent
8c23990949
commit
cd8cb5377a
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@ -695,6 +695,215 @@ entry:
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ret i64 %spec.store.select8
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ret i64 %spec.store.select8
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}
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}
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define i32 @ashrA(i64 %a, i32 %b) {
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; CHECK-LABEL: @ashrA(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = ashr i64 [[A:%.*]], 32
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; CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV]], [[CONV1]]
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; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
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; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648)
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; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
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; CHECK-NEXT: ret i32 [[CONV7]]
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;
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entry:
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%conv = ashr i64 %a, 32
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%conv1 = sext i32 %b to i64
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%add = add i64 %conv1, %conv
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%spec.store.select = call i64 @llvm.smin.i64(i64 %add, i64 2147483647)
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%spec.store.select8 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 -2147483648)
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%conv7 = trunc i64 %spec.store.select8 to i32
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ret i32 %conv7
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}
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define i32 @ashrB(i32 %a, i64 %b) {
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; CHECK-LABEL: @ashrB(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[CONV1:%.*]] = ashr i64 [[B:%.*]], 32
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]]
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; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i64 [[ADD]], -2147483648
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; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select i1 [[TMP0]], i64 [[ADD]], i64 -2147483648
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i64 [[SPEC_STORE_SELECT]], 2147483647
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; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = select i1 [[TMP1]], i64 [[SPEC_STORE_SELECT]], i64 2147483647
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; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
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; CHECK-NEXT: ret i32 [[CONV7]]
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;
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entry:
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%conv = sext i32 %a to i64
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%conv1 = ashr i64 %b, 32
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%add = add i64 %conv1, %conv
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%0 = icmp sgt i64 %add, -2147483648
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%spec.store.select = select i1 %0, i64 %add, i64 -2147483648
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%1 = icmp slt i64 %spec.store.select, 2147483647
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%spec.store.select8 = select i1 %1, i64 %spec.store.select, i64 2147483647
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%conv7 = trunc i64 %spec.store.select8 to i32
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ret i32 %conv7
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}
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define i32 @ashrAB(i64 %a, i64 %b) {
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; CHECK-LABEL: @ashrAB(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = ashr i64 [[A:%.*]], 32
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; CHECK-NEXT: [[CONV1:%.*]] = ashr i64 [[B:%.*]], 32
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]]
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; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i64 [[ADD]], -2147483648
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; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select i1 [[TMP0]], i64 [[ADD]], i64 -2147483648
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i64 [[SPEC_STORE_SELECT]], 2147483647
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; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = select i1 [[TMP1]], i64 [[SPEC_STORE_SELECT]], i64 2147483647
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; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
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; CHECK-NEXT: ret i32 [[CONV7]]
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;
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entry:
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%conv = ashr i64 %a, 32
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%conv1 = ashr i64 %b, 32
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%add = add i64 %conv1, %conv
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%0 = icmp sgt i64 %add, -2147483648
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%spec.store.select = select i1 %0, i64 %add, i64 -2147483648
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%1 = icmp slt i64 %spec.store.select, 2147483647
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%spec.store.select8 = select i1 %1, i64 %spec.store.select, i64 2147483647
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%conv7 = trunc i64 %spec.store.select8 to i32
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ret i32 %conv7
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}
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define i32 @ashrA31(i64 %a, i32 %b) {
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; CHECK-LABEL: @ashrA31(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = ashr i64 [[A:%.*]], 31
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; CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV]], [[CONV1]]
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; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i64 [[ADD]], -2147483648
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; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select i1 [[TMP0]], i64 [[ADD]], i64 -2147483648
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i64 [[SPEC_STORE_SELECT]], 2147483647
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; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = select i1 [[TMP1]], i64 [[SPEC_STORE_SELECT]], i64 2147483647
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; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
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; CHECK-NEXT: ret i32 [[CONV7]]
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;
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entry:
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%conv = ashr i64 %a, 31
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%conv1 = sext i32 %b to i64
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%add = add i64 %conv1, %conv
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%0 = icmp sgt i64 %add, -2147483648
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%spec.store.select = select i1 %0, i64 %add, i64 -2147483648
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%1 = icmp slt i64 %spec.store.select, 2147483647
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%spec.store.select8 = select i1 %1, i64 %spec.store.select, i64 2147483647
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%conv7 = trunc i64 %spec.store.select8 to i32
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ret i32 %conv7
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}
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define i32 @ashrA33(i64 %a, i32 %b) {
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; CHECK-LABEL: @ashrA33(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = ashr i64 [[A:%.*]], 33
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; CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV]], [[CONV1]]
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; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i64 [[ADD]], -2147483648
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; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select i1 [[TMP0]], i64 [[ADD]], i64 -2147483648
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i64 [[SPEC_STORE_SELECT]], 2147483647
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; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = select i1 [[TMP1]], i64 [[SPEC_STORE_SELECT]], i64 2147483647
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; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
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; CHECK-NEXT: ret i32 [[CONV7]]
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;
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entry:
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%conv = ashr i64 %a, 33
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%conv1 = sext i32 %b to i64
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%add = add i64 %conv1, %conv
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%0 = icmp sgt i64 %add, -2147483648
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%spec.store.select = select i1 %0, i64 %add, i64 -2147483648
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%1 = icmp slt i64 %spec.store.select, 2147483647
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%spec.store.select8 = select i1 %1, i64 %spec.store.select, i64 2147483647
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%conv7 = trunc i64 %spec.store.select8 to i32
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ret i32 %conv7
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}
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define <2 x i8> @ashrv2i8(<2 x i16> %a, <2 x i8> %b) {
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; CHECK-LABEL: @ashrv2i8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = ashr <2 x i16> [[A:%.*]], <i16 8, i16 12>
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; CHECK-NEXT: [[CONV1:%.*]] = sext <2 x i8> [[B:%.*]] to <2 x i16>
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; CHECK-NEXT: [[ADD:%.*]] = add <2 x i16> [[CONV]], [[CONV1]]
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; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt <2 x i16> [[ADD]], <i16 -128, i16 -128>
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; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select <2 x i1> [[TMP0]], <2 x i16> [[ADD]], <2 x i16> <i16 -128, i16 -128>
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i16> [[SPEC_STORE_SELECT]], <i16 127, i16 127>
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; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[SPEC_STORE_SELECT]], <2 x i16> <i16 127, i16 127>
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; CHECK-NEXT: [[CONV7:%.*]] = trunc <2 x i16> [[SPEC_STORE_SELECT8]] to <2 x i8>
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; CHECK-NEXT: ret <2 x i8> [[CONV7]]
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;
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entry:
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%conv = ashr <2 x i16> %a, <i16 8, i16 12>
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%conv1 = sext <2 x i8> %b to <2 x i16>
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%add = add <2 x i16> %conv1, %conv
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%0 = icmp sgt <2 x i16> %add, <i16 -128, i16 -128>
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%spec.store.select = select <2 x i1> %0, <2 x i16> %add, <2 x i16> <i16 -128, i16 -128>
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%1 = icmp slt <2 x i16> %spec.store.select, <i16 127, i16 127>
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%spec.store.select8 = select <2 x i1> %1, <2 x i16> %spec.store.select, <2 x i16> <i16 127, i16 127>
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%conv7 = trunc <2 x i16> %spec.store.select8 to <2 x i8>
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ret <2 x i8> %conv7
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}
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define <2 x i8> @ashrv2i8_s(<2 x i16> %a, <2 x i8> %b) {
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; CHECK-LABEL: @ashrv2i8_s(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = ashr <2 x i16> [[A:%.*]], <i16 8, i16 8>
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; CHECK-NEXT: [[CONV1:%.*]] = sext <2 x i8> [[B:%.*]] to <2 x i16>
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; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i16> [[CONV]], [[CONV1]]
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; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt <2 x i16> [[ADD]], <i16 -128, i16 -128>
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; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select <2 x i1> [[TMP0]], <2 x i16> [[ADD]], <2 x i16> <i16 -128, i16 -128>
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i16> [[SPEC_STORE_SELECT]], <i16 127, i16 127>
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; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[SPEC_STORE_SELECT]], <2 x i16> <i16 127, i16 127>
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; CHECK-NEXT: [[CONV7:%.*]] = trunc <2 x i16> [[SPEC_STORE_SELECT8]] to <2 x i8>
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; CHECK-NEXT: ret <2 x i8> [[CONV7]]
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;
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entry:
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%conv = ashr <2 x i16> %a, <i16 8, i16 8>
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%conv1 = sext <2 x i8> %b to <2 x i16>
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%add = add <2 x i16> %conv1, %conv
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%0 = icmp sgt <2 x i16> %add, <i16 -128, i16 -128>
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%spec.store.select = select <2 x i1> %0, <2 x i16> %add, <2 x i16> <i16 -128, i16 -128>
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%1 = icmp slt <2 x i16> %spec.store.select, <i16 127, i16 127>
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%spec.store.select8 = select <2 x i1> %1, <2 x i16> %spec.store.select, <2 x i16> <i16 127, i16 127>
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%conv7 = trunc <2 x i16> %spec.store.select8 to <2 x i8>
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ret <2 x i8> %conv7
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}
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define i16 @or(i8 %X, i16 %Y) {
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; CHECK-LABEL: @or(
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; CHECK-NEXT: [[CONV10:%.*]] = sext i8 [[X:%.*]] to i16
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; CHECK-NEXT: [[CONV14:%.*]] = or i16 [[Y:%.*]], -16
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i16 [[CONV10]], [[CONV14]]
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; CHECK-NEXT: [[L9:%.*]] = icmp sgt i16 [[SUB]], -128
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; CHECK-NEXT: [[L10:%.*]] = select i1 [[L9]], i16 [[SUB]], i16 -128
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; CHECK-NEXT: [[L11:%.*]] = icmp slt i16 [[L10]], 127
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; CHECK-NEXT: [[L12:%.*]] = select i1 [[L11]], i16 [[L10]], i16 127
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; CHECK-NEXT: ret i16 [[L12]]
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;
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%conv10 = sext i8 %X to i16
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%conv14 = or i16 %Y, 65520
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%sub = sub nsw i16 %conv10, %conv14
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%l9 = icmp sgt i16 %sub, -128
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%l10 = select i1 %l9, i16 %sub, i16 -128
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%l11 = icmp slt i16 %l10, 127
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%l12 = select i1 %l11, i16 %l10, i16 127
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ret i16 %l12
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}
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define i16 @const(i8 %X) {
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; CHECK-LABEL: @const(
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; CHECK-NEXT: [[CONV10:%.*]] = sext i8 [[X:%.*]] to i16
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i16 [[CONV10]], 117
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i16 [[CONV10]], i16 117
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; CHECK-NEXT: [[L12:%.*]] = add nsw i16 [[TMP2]], 10
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; CHECK-NEXT: ret i16 [[L12]]
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;
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%conv10 = sext i8 %X to i16
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%sub = add i16 %conv10, 10
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%l9 = icmp sgt i16 %sub, -128
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%l10 = select i1 %l9, i16 %sub, i16 -128
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%l11 = icmp slt i16 %l10, 127
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%l12 = select i1 %l11, i16 %l10, i16 127
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ret i16 %l12
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}
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declare void @use64(i64)
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declare void @use64(i64)
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declare i64 @llvm.smin.i64(i64, i64)
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declare i64 @llvm.smin.i64(i64, i64)
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declare i64 @llvm.smax.i64(i64, i64)
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declare i64 @llvm.smax.i64(i64, i64)
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