forked from OSchip/llvm-project
parent
22e939a15b
commit
cd83d459bc
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@ -285,7 +285,7 @@ void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL,
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// Special case 1, all registers used by ISEL are the same one.
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if (!IsADDIInstRequired && !IsORIInstRequired) {
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LLVM_DEBUG(dbgs() << "Remove redudant ISEL instruction.");
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LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction.");
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// FIXME: if the CR field used has no other uses, we could eliminate the
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// instruction that defines it. This would have to be done manually
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// since this pass runs too late to run DCE after it.
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@ -305,7 +305,7 @@ void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL,
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// thereby preventing this ISEL from being folded.
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if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) {
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LLVM_DEBUG(
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dbgs() << "Fold the ISEL instruction to an unconditonal copy.");
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dbgs() << "Fold the ISEL instruction to an unconditional copy.");
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NumFolded++;
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// Note: we're using both the TrueValue and FalseValue operands so as
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// not to lose the kill flag if it is set on either of them.
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@ -67,7 +67,7 @@ static void updatePHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB,
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for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {
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MachineOperand &MO = MI.getOperand(i);
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if (MO.getMBB() == OrigMBB) {
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// Check if the instruction is actualy defined in NewMBB.
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// Check if the instruction is actually defined in NewMBB.
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if (MI.getOperand(i - 1).isReg()) {
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MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(i - 1).getReg());
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if (DefMI->getParent() == NewMBB ||
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@ -152,7 +152,7 @@ static bool splitMBB(BlockSplitInfo &BSI) {
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if (ThisMBB->succ_size() != 2) {
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LLVM_DEBUG(
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dbgs() << "Don't know how to handle blocks that don't have exactly"
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<< " two succesors.\n");
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<< " two successors.\n");
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return false;
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}
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