forked from OSchip/llvm-project
[AMDGPU] Fix bundle scheduling
Bundles coming to scheduler considered free, i.e. zero latency. Fixed. Differential Revision: https://reviews.llvm.org/D72487
This commit is contained in:
Stanislav Mekhanoshin
parent
b81c8c6976
commit
cd69e4c74c
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@ -755,6 +755,45 @@ struct MemOpClusterMutation : ScheduleDAGMutation {
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}
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};
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struct FixBundleLatencyMutation : ScheduleDAGMutation {
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const SIInstrInfo *TII;
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const TargetSchedModel *TSchedModel;
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FixBundleLatencyMutation(const SIInstrInfo *tii) : TII(tii) {}
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unsigned computeLatency(const MachineInstr &MI, unsigned Reg) const {
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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MachineBasicBlock::const_instr_iterator I(MI.getIterator());
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MachineBasicBlock::const_instr_iterator E(MI.getParent()->instr_end());
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unsigned Lat = 0;
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for (++I; I != E && I->isBundledWithPred(); ++I) {
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if (!I->modifiesRegister(Reg, &TRI))
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continue;
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Lat = TSchedModel->computeInstrLatency(&*I);
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break;
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}
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return Lat;
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}
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void apply(ScheduleDAGInstrs *DAGInstrs) override {
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ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
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TSchedModel = DAGInstrs->getSchedModel();
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if (!TSchedModel || DAG->SUnits.empty())
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return;
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for (SUnit &SU : DAG->SUnits) {
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if (!SU.isInstr() || !SU.getInstr()->isBundle())
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continue;
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for (SDep &Dep : SU.Succs) {
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if (Dep.getKind() == SDep::Kind::Data && Dep.getReg())
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if (unsigned Lat = computeLatency(*SU.getInstr(), Dep.getReg()))
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Dep.setLatency(Lat);
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}
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}
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}
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};
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struct FillMFMAShadowMutation : ScheduleDAGMutation {
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const SIInstrInfo *TII;
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@ -881,6 +920,7 @@ struct FillMFMAShadowMutation : ScheduleDAGMutation {
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void GCNSubtarget::getPostRAMutations(
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std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
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Mutations.push_back(std::make_unique<FixBundleLatencyMutation>(&InstrInfo));
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Mutations.push_back(std::make_unique<MemOpClusterMutation>(&InstrInfo));
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Mutations.push_back(std::make_unique<FillMFMAShadowMutation>(&InstrInfo));
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}
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@ -6625,3 +6625,20 @@ MachineInstr *SIInstrInfo::foldMemoryOperandImpl(
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return nullptr;
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}
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unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr &MI,
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unsigned *PredCost) const {
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if (MI.isBundle()) {
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MachineBasicBlock::const_instr_iterator I(MI.getIterator());
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MachineBasicBlock::const_instr_iterator E(MI.getParent()->instr_end());
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unsigned Lat = 0, Count = 0;
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for (++I; I != E && I->isBundledWithPred(); ++I) {
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++Count;
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Lat = std::max(Lat, getInstrLatency(ItinData, *I, PredCost));
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}
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return Lat + Count - 1;
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}
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return AMDGPUGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
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}
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@ -1042,6 +1042,10 @@ public:
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int FrameIndex,
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LiveIntervals *LIS = nullptr,
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VirtRegMap *VRM = nullptr) const override;
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr &MI,
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unsigned *PredCost) const override;
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};
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/// \brief Returns true if a reg:subreg pair P has a TRC class
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@ -2,7 +2,7 @@
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %s
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; Make sure the op is emitted bundled with a waitcnt with and without the retry loop, and the bundle is not removed by ExpandPostRAPseudos.
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=postrapseudos -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=MIR %s
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@ -2,7 +2,7 @@
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
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; Minimum offset
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; GCN-LABEL: {{^}}gws_init_offset0:
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@ -404,7 +404,7 @@ define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(i32 addrspace(1)* %out0
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; FUNC-LABEL: @v_test_umin_ult_i16_multi_use
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; GCN-NOT: v_min
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; GCN: v_cmp_lt_u32
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; GCN-NEXT: v_cndmask_b32
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; GCN: v_cndmask_b32
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; GCN-NOT: v_min
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; GCN: s_endpgm
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@ -35,12 +35,12 @@ body: |
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# CHECK-DAG: $sgpr8 = S_MOV_B32 3
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# CHECK-DAG: $sgpr33 = S_MOV_B32 $sgpr7
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# CHECK: $vgpr0 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $sgpr8_sgpr9_sgpr10_sgpr11
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# CHECK: $sgpr32 = S_MOV_B32 $sgpr33
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# CHECK: BUNDLE implicit-def $sgpr6_sgpr7, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $scc {
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# CHECK: $sgpr6_sgpr7 = S_GETPC_B64
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# CHECK: $sgpr6 = S_ADD_U32 internal $sgpr6, 0, implicit-def $scc
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# CHECK: $sgpr7 = S_ADDC_U32 internal $sgpr7, 0, implicit-def $scc, implicit internal $scc
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# CHECK: }
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# CHECK: $sgpr32 = S_MOV_B32 $sgpr33
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# CHECK: $sgpr4 = S_MOV_B32 killed $sgpr33
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# CHECK: $vgpr1 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
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# CHECK: $vgpr2 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
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@ -199,10 +199,10 @@ define void @slsr1_1(i32 %b.arg, i32 %s.arg) #0 {
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; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s34 offset:4 ; 4-byte Folded Spill
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; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s34 ; 4-byte Folded Spill
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; GFX9-NEXT: v_writelane_b32 v35, s36, 0
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; GFX9-NEXT: v_writelane_b32 v35, s37, 1
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; GFX9-NEXT: s_getpc_b64 s[4:5]
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; GFX9-NEXT: s_add_u32 s4, s4, foo@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s5, s5, foo@gotpcrel32@hi+4
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; GFX9-NEXT: v_writelane_b32 v35, s37, 1
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; GFX9-NEXT: s_load_dwordx2 s[36:37], s[4:5], 0x0
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; GFX9-NEXT: v_mov_b32_e32 v32, v1
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; GFX9-NEXT: v_mov_b32_e32 v33, v0
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@ -205,7 +205,7 @@ entry:
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; GCN-NOT: and
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; GCN-NOT: lshr
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; GCN: v_mul_hi_u32_u24_e32 v[[MUL_HI:[0-9]+]],
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; GCN-NEXT: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
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; GCN: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
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; GCN-NEXT: buffer_store_dword v[[HI]]
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define amdgpu_kernel void @test_umulhi24_i33(i32 addrspace(1)* %out, i33 %a, i33 %b) {
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entry:
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@ -204,8 +204,8 @@ bb:
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; GCN: ds_read_u16 [[SCALAR1:v[0-9]+]]
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; FIXME: Remove and
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; GCN: v_and_b32_e32 [[SCALAR0]], 0xffff, [[SCALAR0]]
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; GCN: v_xor_b32_e32 [[SCALAR1]], 0x8000, [[SCALAR1]]
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; GCN-DAG: v_and_b32_e32 [[SCALAR0]], 0xffff, [[SCALAR0]]
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; GCN-DAG: v_xor_b32_e32 [[SCALAR1]], 0x8000, [[SCALAR1]]
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; GCN: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[SCALAR1]], 16, [[SCALAR0]]
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; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[PACKED]]{{$}}
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@ -660,7 +660,7 @@ bb:
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; GCN-NOT: _or
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; GCN: v_pk_add_f16 [[FADD:v[0-9]+]]
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; GCN-NEXT: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[FADD]] op_sel:[0,0,1] op_sel_hi:[1,1,0]{{$}}
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; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[FADD]] op_sel:[0,0,1] op_sel_hi:[1,1,0]{{$}}
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define amdgpu_kernel void @mix_elt_types_op_sel(<2 x half> addrspace(1)* %out, <2 x half> addrspace(3)* %lds) #0 {
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bb:
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%lds.gep1 = getelementptr inbounds <2 x half>, <2 x half> addrspace(3)* %lds, i32 1
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@ -22,9 +22,9 @@
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; GFX9-DAG: s_mov_b32 s7, 0xe00000
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; GFX10_W32-DAG: s_mov_b32 s7, 0x31c16000
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; GFX10_W64-DAG: s_mov_b32 s7, 0x31e16000
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; GCN-NOT: s_mov_b32 s0
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; GCN-DAG: v_lshlrev_b32_e32 [[BYTES:v[0-9]+]], 2, v0
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; GCN-DAG: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, [[BYTES]]
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; GCN-NOT: s_mov_b32 s0
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; GCN-DAG: v_or_b32_e32 [[LO_OFF:v[0-9]+]], 0x200, [[CLAMP_IDX]]
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; GCN-DAG: v_or_b32_e32 [[HI_OFF:v[0-9]+]], 0x400, [[CLAMP_IDX]]
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@ -69,7 +69,7 @@ entry:
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; FUNC-LABEL: {{^}}selectcc_bool:
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; SI: v_cmp_ne_u32
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; SI-NEXT: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI-NOT: cmp
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; SI-NOT: cndmask
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define amdgpu_kernel void @selectcc_bool(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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@ -5,7 +5,7 @@
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; FUNC-LABEL: {{^}}sext_bool_icmp_eq_0:
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; GCN-NOT: v_cmp
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; GCN: v_cmp_ne_u32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN-NEXT:buffer_store_byte [[RESULT]]
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; GCN-NEXT: s_endpgm
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@ -22,7 +22,7 @@ define amdgpu_kernel void @sext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i3
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; FUNC-LABEL: {{^}}sext_bool_icmp_ne_0:
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; GCN-NOT: v_cmp
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; GCN: v_cmp_ne_u32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN-NEXT: buffer_store_byte [[RESULT]]
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; GCN-NEXT: s_endpgm
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@ -39,7 +39,7 @@ define amdgpu_kernel void @sext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i3
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; FUNC-LABEL: {{^}}sext_bool_icmp_eq_neg1:
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; GCN-NOT: v_cmp
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; GCN: v_cmp_eq_u32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN-NEXT: buffer_store_byte [[RESULT]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @sext_bool_icmp_eq_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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@ -53,7 +53,7 @@ define amdgpu_kernel void @sext_bool_icmp_eq_neg1(i1 addrspace(1)* %out, i32 %a,
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; FUNC-LABEL: {{^}}sext_bool_icmp_ne_neg1:
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; GCN-NOT: v_cmp
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; GCN: v_cmp_eq_u32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN-NEXT: buffer_store_byte [[RESULT]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @sext_bool_icmp_ne_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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@ -67,7 +67,7 @@ define amdgpu_kernel void @sext_bool_icmp_ne_neg1(i1 addrspace(1)* %out, i32 %a,
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; FUNC-LABEL: {{^}}zext_bool_icmp_eq_0:
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; GCN-NOT: v_cmp
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; GCN: v_cmp_ne_u32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN-NEXT: buffer_store_byte [[RESULT]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @zext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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@ -81,7 +81,7 @@ define amdgpu_kernel void @zext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i3
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; FUNC-LABEL: {{^}}zext_bool_icmp_ne_0:
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; GCN-NOT: v_cmp
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; GCN: v_cmp_ne_u32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN-NEXT: buffer_store_byte [[RESULT]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @zext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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@ -95,7 +95,7 @@ define amdgpu_kernel void @zext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i3
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; FUNC-LABEL: {{^}}zext_bool_icmp_eq_1:
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; GCN-NOT: v_cmp
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; GCN: v_cmp_eq_u32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN-NEXT: buffer_store_byte [[RESULT]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @zext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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@ -109,7 +109,7 @@ define amdgpu_kernel void @zext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i3
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; FUNC-LABEL: {{^}}zext_bool_icmp_ne_1:
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; GCN-NOT: v_cmp
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; GCN: v_cmp_eq_u32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN-NEXT: buffer_store_byte [[RESULT]]
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define amdgpu_kernel void @zext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%icmp0 = icmp ne i32 %a, %b
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@ -78,7 +78,7 @@ define amdgpu_kernel void @v_sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4
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; FUNC-LABEL: {{^}}s_sint_to_fp_i1_f32:
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; SI: v_cmp_eq_u32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
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; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
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; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define amdgpu_kernel void @s_sint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) #0 {
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@ -59,7 +59,7 @@ define amdgpu_kernel void @max_10_vgprs(i32 addrspace(1)* %p) #0 {
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; GCN-LABEL: {{^}}max_10_vgprs_used_9a:
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; GFX908-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; GFX908-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; GFX908: v_accvgpr_write_b32 a9, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a9, v{{[0-9]}}
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; GFX908: buffer_store_dword v{{[0-9]}},
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; GFX908-NOT: buffer_
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; GFX908: v_accvgpr_read_b32 v{{[0-9]}}, a9
|
||||
|
|
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|||
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|
@ -108,7 +108,7 @@ define amdgpu_kernel void @v_test_sub_i16_zext_to_i64(i64 addrspace(1)* %out, i1
|
|||
; VI: flat_load_ushort [[A:v[0-9]+]]
|
||||
; VI: flat_load_ushort [[B:v[0-9]+]]
|
||||
; VI: v_sub_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
|
||||
; VI-NEXT: v_bfe_i32 [[SEXT:v[0-9]+]], [[ADD]], 0, 16
|
||||
; VI: v_bfe_i32 [[SEXT:v[0-9]+]], [[ADD]], 0, 16
|
||||
; VI-NEXT: buffer_store_dword [[SEXT]]
|
||||
define amdgpu_kernel void @v_test_sub_i16_sext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
|
@ -129,7 +129,7 @@ define amdgpu_kernel void @v_test_sub_i16_sext_to_i32(i32 addrspace(1)* %out, i1
|
|||
; VI: flat_load_ushort [[B:v[0-9]+]]
|
||||
; VI: v_sub_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
|
||||
; VI-NEXT: v_bfe_i32 v[[LO:[0-9]+]], [[ADD]], 0, 16
|
||||
; VI-NEXT: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
|
||||
; VI: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
|
||||
; VI-NEXT: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
|
||||
define amdgpu_kernel void @v_test_sub_i16_sext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ define amdgpu_kernel void @v_uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4
|
|||
|
||||
; FUNC-LABEL: {{^}}s_uint_to_fp_i1_to_f32:
|
||||
; SI: v_cmp_eq_u32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
|
||||
; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
|
||||
; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
|
||||
; SI: buffer_store_dword [[RESULT]],
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @s_uint_to_fp_i1_to_f32(float addrspace(1)* %out, i32 %in) #0 {
|
||||
|
|
|
|||
|
|
@ -491,10 +491,10 @@ entry:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_br_cc_f16:
|
||||
; GFX1032: v_cmp_nlt_f16_e32 vcc_lo,
|
||||
; GFX1032-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
|
||||
; GFX1064: v_cmp_nlt_f16_e32 vcc,
|
||||
; GFX1064-NEXT: s_and_b64 vcc, exec, vcc{{$}}
|
||||
; GFX1032: v_cmp_nlt_f16_e32 vcc_lo,
|
||||
; GFX1032: s_and_b32 vcc_lo, exec_lo, vcc_lo
|
||||
; GFX1064: v_cmp_nlt_f16_e32 vcc,
|
||||
; GFX1064: s_and_b64 vcc, exec, vcc{{$}}
|
||||
; GCN-NEXT: s_cbranch_vccnz
|
||||
define amdgpu_kernel void @test_br_cc_f16(
|
||||
half addrspace(1)* %r,
|
||||
|
|
|
|||
|
|
@ -36,9 +36,9 @@ define amdgpu_kernel void @s_arg_zext_i1_to_i64(i64 addrspace(1)* %out, i1 zeroe
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i64:
|
||||
; GCN: s_mov_b32 s{{[0-9]+}}, 0
|
||||
; GCN: v_cmp_eq_u32
|
||||
; GCN: v_cndmask_b32
|
||||
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, 0
|
||||
; GCN-DAG: v_cmp_eq_u32
|
||||
; GCN: v_cndmask_b32
|
||||
define amdgpu_kernel void @s_cmp_zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%cmp = icmp eq i32 %a, %b
|
||||
%ext = zext i1 %cmp to i64
|
||||
|
|
|
|||
Loading…
Reference in New Issue