diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap.ll b/llvm/test/CodeGen/RISCV/shrinkwrap.ll
index 1eaa02462336..7ae677ba1f24 100644
--- a/llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ b/llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,4 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap=false < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I-SW-NO
 ; RUN: llc -mtriple riscv32 < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I-SW
 ; RUN: llc -mtriple riscv32 -mattr=+save-restore < %s \
@@ -9,6 +11,19 @@
 declare void @abort()
 
 define void @eliminate_restore(i32 %n) nounwind {
+; RV32I-SW-NO-LABEL: eliminate_restore:
+; RV32I-SW-NO:       # %bb.0:
+; RV32I-SW-NO-NEXT:    addi sp, sp, -16
+; RV32I-SW-NO-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-SW-NO-NEXT:    addi a1, zero, 32
+; RV32I-SW-NO-NEXT:    bgeu a1, a0, .LBB0_2
+; RV32I-SW-NO-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-NO-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-SW-NO-NEXT:    addi sp, sp, 16
+; RV32I-SW-NO-NEXT:    ret
+; RV32I-SW-NO-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-NO-NEXT:    call abort@plt
+;
 ; RV32I-SW-LABEL: eliminate_restore:
 ; RV32I-SW:       # %bb.0:
 ; RV32I-SW-NEXT:    addi a1, zero, 32
@@ -55,6 +70,27 @@ if.end:
 declare void @notdead(i8*)
 
 define void @conditional_alloca(i32 %n) nounwind {
+; RV32I-SW-NO-LABEL: conditional_alloca:
+; RV32I-SW-NO:       # %bb.0:
+; RV32I-SW-NO-NEXT:    addi sp, sp, -16
+; RV32I-SW-NO-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-SW-NO-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-SW-NO-NEXT:    addi s0, sp, 16
+; RV32I-SW-NO-NEXT:    addi a1, zero, 32
+; RV32I-SW-NO-NEXT:    bltu a1, a0, .LBB1_2
+; RV32I-SW-NO-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-NO-NEXT:    addi a0, a0, 15
+; RV32I-SW-NO-NEXT:    andi a0, a0, -16
+; RV32I-SW-NO-NEXT:    sub a0, sp, a0
+; RV32I-SW-NO-NEXT:    mv sp, a0
+; RV32I-SW-NO-NEXT:    call notdead@plt
+; RV32I-SW-NO-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-NO-NEXT:    addi sp, s0, -16
+; RV32I-SW-NO-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-SW-NO-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-SW-NO-NEXT:    addi sp, sp, 16
+; RV32I-SW-NO-NEXT:    ret
+;
 ; RV32I-SW-LABEL: conditional_alloca:
 ; RV32I-SW:       # %bb.0:
 ; RV32I-SW-NEXT:    addi a1, zero, 32