forked from OSchip/llvm-project
[ARM] Avoid pointless vrev of element-wise vmov
If we have an element-wise vmov immediate instruction then a subsequent vrev with width greater or equal to the vmov element width, then that vrev won't do anything. Add a DAG combine to convert bitcasts that would become such vrevs into vector_reg_casts instead. Differential Revision: https://reviews.llvm.org/D76514
This commit is contained in:
John Brawn
parent
966ae76222
commit
cd58fb6325
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@ -943,6 +943,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::INTRINSIC_VOID);
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setTargetDAGCombine(ISD::VECREDUCE_ADD);
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::BITCAST);
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}
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if (!Subtarget->hasFP64()) {
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@ -9223,9 +9224,10 @@ static SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) {
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N->getMemoryVT(), N->getMemOperand(), N->getAddressingMode(),
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N->getExtensionType(), N->isExpandingLoad());
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SDValue Combo = NewLoad;
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if (!PassThru.isUndef() &&
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(PassThru.getOpcode() != ISD::BITCAST ||
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!isZeroVector(PassThru->getOperand(0))))
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bool PassThruIsCastZero = (PassThru.getOpcode() == ISD::BITCAST ||
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PassThru.getOpcode() == ARMISD::VECTOR_REG_CAST) &&
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isZeroVector(PassThru->getOperand(0));
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if (!PassThru.isUndef() && !PassThruIsCastZero)
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Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru);
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return DAG.getMergeValues({Combo, NewLoad.getValue(1)}, dl);
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}
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@ -15211,6 +15213,28 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
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return Res;
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}
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static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
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SDValue Src = N->getOperand(0);
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// We may have a bitcast of something that has already had this bitcast
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// combine performed on it, so skip past any VECTOR_REG_CASTs.
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while (Src.getOpcode() == ARMISD::VECTOR_REG_CAST)
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Src = Src.getOperand(0);
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// Bitcast from element-wise VMOV or VMVN doesn't need VREV if the VREV that
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// would be generated is at least the width of the element type.
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EVT SrcVT = Src.getValueType();
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EVT DstVT = N->getValueType(0);
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if ((Src.getOpcode() == ARMISD::VMOVIMM ||
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Src.getOpcode() == ARMISD::VMVNIMM ||
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Src.getOpcode() == ARMISD::VMOVFPIMM) &&
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SrcVT.getScalarSizeInBits() <= DstVT.getScalarSizeInBits() &&
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DAG.getDataLayout().isBigEndian())
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return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(N), DstVT, Src);
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return SDValue();
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}
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SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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switch (N->getOpcode()) {
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@ -15264,6 +15288,8 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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return PerformVLDCombine(N, DCI);
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case ARMISD::BUILD_VECTOR:
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return PerformARMBUILD_VECTORCombine(N, DCI);
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case ISD::BITCAST:
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return PerformBITCASTCombine(N, DCI.DAG);
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case ARMISD::PREDICATE_CAST:
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return PerformPREDICATE_CASTCombine(N, DCI);
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case ARMISD::VECTOR_REG_CAST:
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File diff suppressed because it is too large
Load Diff
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@ -1830,8 +1830,7 @@ define arm_aapcs_vfpcc <2 x i64> @masked_v2i64_align4_zero(<2 x i64> *%dest, <2
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; CHECK-BE-NEXT: vldr d0, [r0]
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; CHECK-BE-NEXT: b .LBB49_3
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; CHECK-BE-NEXT: .LBB49_2:
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; CHECK-BE-NEXT: vmov.i32 q1, #0x0
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; CHECK-BE-NEXT: vrev64.32 q0, q1
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; CHECK-BE-NEXT: vmov.i32 q0, #0x0
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; CHECK-BE-NEXT: .LBB49_3: @ %else
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; CHECK-BE-NEXT: lsls r1, r1, #30
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; CHECK-BE-NEXT: it mi
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@ -1924,8 +1923,7 @@ define arm_aapcs_vfpcc <2 x double> @masked_v2f64_align4_zero(<2 x double> *%des
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; CHECK-BE-NEXT: vldr d0, [r0]
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; CHECK-BE-NEXT: b .LBB50_3
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; CHECK-BE-NEXT: .LBB50_2:
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; CHECK-BE-NEXT: vmov.i32 q1, #0x0
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; CHECK-BE-NEXT: vrev64.32 q0, q1
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; CHECK-BE-NEXT: vmov.i32 q0, #0x0
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; CHECK-BE-NEXT: .LBB50_3: @ %else
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; CHECK-BE-NEXT: lsls r1, r1, #30
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; CHECK-BE-NEXT: it mi
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@ -4,91 +4,55 @@
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; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKBE
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define arm_aapcs_vfpcc <16 x i8> @mov_int8_1() {
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; CHECKLE-LABEL: mov_int8_1:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i8 q0, #0x1
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int8_1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i8 q1, #0x1
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int8_1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q0, #0x1
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; CHECK-NEXT: bx lr
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entry:
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ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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}
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define arm_aapcs_vfpcc <16 x i8> @mov_int8_m1() {
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; CHECKLE-LABEL: mov_int8_m1:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i8 q0, #0xff
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int8_m1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i8 q1, #0xff
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int8_m1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q0, #0xff
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; CHECK-NEXT: bx lr
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entry:
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ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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}
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define arm_aapcs_vfpcc <8 x i16> @mov_int16_1() {
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; CHECKLE-LABEL: mov_int16_1:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i16 q0, #0x1
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int16_1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i16 q1, #0x1
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; CHECKBE-NEXT: vrev64.16 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int16_1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q0, #0x1
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; CHECK-NEXT: bx lr
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entry:
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ret <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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}
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define arm_aapcs_vfpcc <8 x i16> @mov_int16_m1() {
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; CHECKLE-LABEL: mov_int16_m1:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i8 q0, #0xff
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int16_m1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i8 q1, #0xff
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int16_m1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q0, #0xff
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; CHECK-NEXT: bx lr
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entry:
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ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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}
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define arm_aapcs_vfpcc <8 x i16> @mov_int16_256() {
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; CHECKLE-LABEL: mov_int16_256:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i16 q0, #0x100
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int16_256:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i16 q1, #0x100
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; CHECKBE-NEXT: vrev64.16 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int16_256:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q0, #0x100
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; CHECK-NEXT: bx lr
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entry:
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ret <8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
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}
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define arm_aapcs_vfpcc <8 x i16> @mov_int16_257() {
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; CHECKLE-LABEL: mov_int16_257:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i8 q0, #0x1
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int16_257:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i8 q1, #0x1
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int16_257:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q0, #0x1
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; CHECK-NEXT: bx lr
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entry:
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ret <8 x i16> <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
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}
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@ -125,61 +89,37 @@ entry:
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}
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_1() {
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; CHECKLE-LABEL: mov_int32_1:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i32 q0, #0x1
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int32_1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i32 q1, #0x1
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; CHECKBE-NEXT: vrev64.32 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int32_1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q0, #0x1
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; CHECK-NEXT: bx lr
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entry:
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ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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}
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_256() {
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; CHECKLE-LABEL: mov_int32_256:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i32 q0, #0x100
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int32_256:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i32 q1, #0x100
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; CHECKBE-NEXT: vrev64.32 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int32_256:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q0, #0x100
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; CHECK-NEXT: bx lr
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entry:
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ret <4 x i32> <i32 256, i32 256, i32 256, i32 256>
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}
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_65536() {
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; CHECKLE-LABEL: mov_int32_65536:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i32 q0, #0x10000
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int32_65536:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i32 q1, #0x10000
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; CHECKBE-NEXT: vrev64.32 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int32_65536:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q0, #0x10000
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; CHECK-NEXT: bx lr
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entry:
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ret <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>
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}
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777216() {
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; CHECKLE-LABEL: mov_int32_16777216:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i32 q0, #0x1000000
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int32_16777216:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i32 q1, #0x1000000
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; CHECKBE-NEXT: vrev64.32 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int32_16777216:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q0, #0x1000000
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; CHECK-NEXT: bx lr
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entry:
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ret <4 x i32> <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
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}
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@ -216,61 +156,37 @@ entry:
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}
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_17919() {
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; CHECKLE-LABEL: mov_int32_17919:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i32 q0, #0x45ff
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int32_17919:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i32 q1, #0x45ff
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; CHECKBE-NEXT: vrev64.32 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int32_17919:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q0, #0x45ff
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; CHECK-NEXT: bx lr
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entry:
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ret <4 x i32> <i32 17919, i32 17919, i32 17919, i32 17919>
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}
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_4587519() {
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; CHECKLE-LABEL: mov_int32_4587519:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i32 q0, #0x45ffff
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int32_4587519:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i32 q1, #0x45ffff
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; CHECKBE-NEXT: vrev64.32 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int32_4587519:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q0, #0x45ffff
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; CHECK-NEXT: bx lr
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entry:
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ret <4 x i32> <i32 4587519, i32 4587519, i32 4587519, i32 4587519>
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}
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_m1() {
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; CHECKLE-LABEL: mov_int32_m1:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmov.i8 q0, #0xff
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int32_m1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmov.i8 q1, #0xff
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int32_m1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q0, #0xff
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; CHECK-NEXT: bx lr
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entry:
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ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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}
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_4294901760() {
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; CHECKLE-LABEL: mov_int32_4294901760:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: vmvn.i32 q0, #0xffff
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; CHECKLE-NEXT: bx lr
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;
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; CHECKBE-LABEL: mov_int32_4294901760:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vmvn.i32 q1, #0xffff
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; CHECKBE-NEXT: vrev64.32 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECK-LABEL: mov_int32_4294901760:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmvn.i32 q0, #0xffff
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; CHECK-NEXT: bx lr
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entry:
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ret <4 x i32> <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
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||||
}
|
||||
|
|
@ -307,16 +223,10 @@ entry:
|
|||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278255615() {
|
||||
; CHECKLE-LABEL: mov_int32_4278255615:
|
||||
; CHECKLE: @ %bb.0: @ %entry
|
||||
; CHECKLE-NEXT: vmvn.i32 q0, #0xff0000
|
||||
; CHECKLE-NEXT: bx lr
|
||||
;
|
||||
; CHECKBE-LABEL: mov_int32_4278255615:
|
||||
; CHECKBE: @ %bb.0: @ %entry
|
||||
; CHECKBE-NEXT: vmvn.i32 q1, #0xff0000
|
||||
; CHECKBE-NEXT: vrev64.32 q0, q1
|
||||
; CHECKBE-NEXT: bx lr
|
||||
; CHECK-LABEL: mov_int32_4278255615:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmvn.i32 q0, #0xff0000
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
ret <4 x i32> <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>
|
||||
}
|
||||
|
|
@ -367,16 +277,10 @@ entry:
|
|||
}
|
||||
|
||||
define arm_aapcs_vfpcc <2 x i64> @mov_int64_m1() {
|
||||
; CHECKLE-LABEL: mov_int64_m1:
|
||||
; CHECKLE: @ %bb.0: @ %entry
|
||||
; CHECKLE-NEXT: vmov.i8 q0, #0xff
|
||||
; CHECKLE-NEXT: bx lr
|
||||
;
|
||||
; CHECKBE-LABEL: mov_int64_m1:
|
||||
; CHECKBE: @ %bb.0: @ %entry
|
||||
; CHECKBE-NEXT: vmov.i8 q1, #0xff
|
||||
; CHECKBE-NEXT: vrev64.8 q0, q1
|
||||
; CHECKBE-NEXT: bx lr
|
||||
; CHECK-LABEL: mov_int64_m1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.i8 q0, #0xff
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
ret <2 x i64> < i64 -1, i64 -1 >
|
||||
}
|
||||
|
|
@ -462,8 +366,7 @@ define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f0f0f0f0f0f0f0f() {
|
|||
;
|
||||
; CHECKBE-LABEL: mov_int64_0f0f0f0f0f0f0f0f:
|
||||
; CHECKBE: @ %bb.0: @ %entry
|
||||
; CHECKBE-NEXT: vmov.i16 q1, #0xff00
|
||||
; CHECKBE-NEXT: vrev64.16 q0, q1
|
||||
; CHECKBE-NEXT: vmov.i16 q0, #0xff00
|
||||
; CHECKBE-NEXT: bx lr
|
||||
entry:
|
||||
ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>
|
||||
|
|
@ -532,32 +435,20 @@ entry:
|
|||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x half> @mov_float16_1() {
|
||||
; CHECKLE-LABEL: mov_float16_1:
|
||||
; CHECKLE: @ %bb.0: @ %entry
|
||||
; CHECKLE-NEXT: vmov.i16 q0, #0x3c00
|
||||
; CHECKLE-NEXT: bx lr
|
||||
;
|
||||
; CHECKBE-LABEL: mov_float16_1:
|
||||
; CHECKBE: @ %bb.0: @ %entry
|
||||
; CHECKBE-NEXT: vmov.i16 q1, #0x3c00
|
||||
; CHECKBE-NEXT: vrev64.16 q0, q1
|
||||
; CHECKBE-NEXT: bx lr
|
||||
; CHECK-LABEL: mov_float16_1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.i16 q0, #0x3c00
|
||||
; CHECK-NEXT: bx lr
|
||||
|
||||
entry:
|
||||
ret <8 x half> <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00>
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x half> @mov_float16_m3() {
|
||||
; CHECKLE-LABEL: mov_float16_m3:
|
||||
; CHECKLE: @ %bb.0: @ %entry
|
||||
; CHECKLE-NEXT: vmov.i16 q0, #0xc200
|
||||
; CHECKLE-NEXT: bx lr
|
||||
;
|
||||
; CHECKBE-LABEL: mov_float16_m3:
|
||||
; CHECKBE: @ %bb.0: @ %entry
|
||||
; CHECKBE-NEXT: vmov.i16 q1, #0xc200
|
||||
; CHECKBE-NEXT: vrev64.16 q0, q1
|
||||
; CHECKBE-NEXT: bx lr
|
||||
; CHECK-LABEL: mov_float16_m3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.i16 q0, #0xc200
|
||||
; CHECK-NEXT: bx lr
|
||||
|
||||
entry:
|
||||
ret <8 x half> <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00>
|
||||
|
|
|
|||
Loading…
Reference in New Issue