forked from OSchip/llvm-project
[DAG] Fix and-mask folding when narrowing loads.
Summary: Check that and masks are strictly smaller than implicit mask from narrowed load. Fixes PR37820. Reviewers: samparker, RKSimon, nemanjai Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48335 llvm-svn: 335137
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@ -8688,8 +8688,9 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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if (ShiftMask.isMask()) {
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EVT MaskedVT = EVT::getIntegerVT(*DAG.getContext(),
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ShiftMask.countTrailingOnes());
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// Recompute the type.
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if (TLI.isLoadExtLegal(ExtType, N0.getValueType(), MaskedVT))
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// If the mask is smaller, recompute the type.
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if ((ExtVT.getSizeInBits() > MaskedVT.getSizeInBits()) &&
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TLI.isLoadExtLegal(ExtType, N0.getValueType(), MaskedVT))
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ExtVT = MaskedVT;
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}
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}
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@ -0,0 +1,25 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
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@a = external dso_local local_unnamed_addr global i64, align 8
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@c = external dso_local local_unnamed_addr global i64, align 8
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@b = external dso_local local_unnamed_addr global i64, align 8
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; Should generate a 16-bit load
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define void @foo() {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movzwl a+{{.*}}(%rip), %eax
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: retq
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entry:
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%0 = load i64, i64* @a, align 8
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%1 = load i64, i64* @c, align 8
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%and = and i64 %1, -16384
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%add = add nsw i64 %and, 4503359447364223024
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%shr = lshr i64 %0, %add
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%conv1 = and i64 %shr, 4294967295
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store i64 %conv1, i64* @b, align 8
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ret void
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}
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