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Added a way to resolve an load address from a target: 

bool
Address::SetLoadAddress (lldb::addr_t load_addr, Target *target);

Added an == and != operator to RegisterValue.

Modified the ThreadPlanTracer to use RegisterValue objects to store the
register values when single stepping. Also modified the output to be a bit
less wide.

Fixed the ABIMacOSX_arm to not overwrite stuff on the stack. Also made the
trivial function call be able to set the ARM/Thumbness of the target 
correctly, and also sets the return value ARM/Thumbness.

Fixed the encoding on the arm s0-s31 and d16 - d31 registers when the default
register set from a standard GDB server register sets.

llvm-svn: 131517
This commit is contained in:
Greg Clayton 2011-05-18 01:58:14 +00:00
parent 96254a0d53
commit cd482e359e
12 changed files with 266 additions and 105 deletions
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27
lldb/include/lldb/Core/Address.h
View File

@ -356,6 +356,33 @@ public:
void
ResolveLinkedAddress ();
//------------------------------------------------------------------
/// Set the address to represent \a load_addr.
///
/// The address will attempt to find a loaded section within
/// \a target that contains \a load_addr. If successful, this
/// address object will have a valid section and offset. Else this
/// address object will have no section (NULL) and the offset will
/// be \a load_addr.
///
/// @param[in] load_addr
/// A load address from a current process.
///
/// @param[in] target
/// The target to use when trying resolve the address into
/// a section + offset. The Target's SectionLoadList object
/// is used to resolve the address.
///
/// @return
/// Returns \b true if the load address was resolved to be
/// section/offset, \b false otherwise. It is often ok for an
/// address no not resolve to a section in a module, this often
/// happens for JIT'ed code, or any load addresses on the stack
/// or heap.
//------------------------------------------------------------------
bool
SetLoadAddress (lldb::addr_t load_addr, Target *target);
//------------------------------------------------------------------
/// Get accessor for the module for this address.
///

6
lldb/include/lldb/Core/RegisterValue.h
View File

@ -197,6 +197,12 @@ namespace lldb_private {
m_type = eTypeInvalid;
}
bool
operator == (const RegisterValue &rhs) const;
bool
operator != (const RegisterValue &rhs) const;
void
operator = (uint8_t uint)
{

2
lldb/include/lldb/Target/Process.h
View File

@ -2184,6 +2184,8 @@ public:
/// that a block that isn't set writable can still be written on from lldb,
/// just not by the process itself.
///
/// @param[in/out] error
/// An error object to fill in if things go wrong.
/// @return
/// The address of the allocated buffer in the process, or
/// LLDB_INVALID_ADDRESS if the allocation failed.

3
lldb/include/lldb/Target/ThreadPlanTracer.h
View File

@ -15,6 +15,7 @@
// Other libraries and framework includes
// Project includes
#include "lldb/lldb-private.h"
#include "lldb/Core/RegisterValue.h"
#include "lldb/Symbol/TaggedASTType.h"
#include "lldb/Target/Thread.h"
@ -117,7 +118,7 @@ private:
Disassembler *m_disassembler;
const ABI *m_abi;
TypeFromUser m_intptr_type;
std::vector<uint64_t> m_register_values;
std::vector<RegisterValue> m_register_values;
lldb::DataBufferSP m_buffer_sp;
};

11
lldb/source/Core/Address.cpp
View File

@ -821,3 +821,14 @@ Address::GetAddressClass () const
}
return eAddressClassUnknown;
}
bool
Address::SetLoadAddress (lldb::addr_t load_addr, Target *target)
{
if (target && target->GetSectionLoadList().ResolveLoadAddress(load_addr, *this))
return true;
m_section = NULL;
m_offset = load_addr;
return false;
}

72
lldb/source/Core/RegisterValue.cpp
View File

@ -73,7 +73,7 @@ RegisterValue::Dump (Stream *s,
data.Dump (s,
0, // Offset in "data"
format, // Format to use when dumping
reg_info->byte_size, // item_byte_size
reg_info->byte_size, // item_byte_size
1, // item_count
UINT32_MAX, // num_per_line
LLDB_INVALID_ADDRESS, // base_addr
@ -930,3 +930,73 @@ RegisterValue::SetBytes (const void *bytes, size_t length, lldb::ByteOrder byte_
}
}
bool
RegisterValue::operator == (const RegisterValue &rhs) const
{
if (m_type == rhs.m_type)
{
switch (m_type)
{
case eTypeInvalid: return true;
case eTypeUInt8: return m_data.uint8 == rhs.m_data.uint8;
case eTypeUInt16: return m_data.uint16 == rhs.m_data.uint16;
case eTypeUInt32: return m_data.uint32 == rhs.m_data.uint32;
case eTypeUInt64: return m_data.uint64 == rhs.m_data.uint64;
#if defined (ENABLE_128_BIT_SUPPORT)
case eTypeUInt128: return m_data.uint128 == rhs.m_data.uint128;
#endif
case eTypeFloat: return m_data.ieee_float == rhs.m_data.ieee_float;
case eTypeDouble: return m_data.ieee_double == rhs.m_data.ieee_double;
case eTypeLongDouble: return m_data.ieee_long_double == rhs.m_data.ieee_long_double;
case eTypeBytes:
if (m_data.buffer.length != rhs.m_data.buffer.length)
return false;
else
{
uint8_t length = m_data.buffer.length;
if (length > kMaxRegisterByteSize)
length = kMaxRegisterByteSize;
return memcmp (m_data.buffer.bytes, rhs.m_data.buffer.bytes, length) == 0;
}
break;
}
}
return false;
}
bool
RegisterValue::operator != (const RegisterValue &rhs) const
{
if (m_type != rhs.m_type)
return true;
switch (m_type)
{
case eTypeInvalid: return false;
case eTypeUInt8: return m_data.uint8 != rhs.m_data.uint8;
case eTypeUInt16: return m_data.uint16 != rhs.m_data.uint16;
case eTypeUInt32: return m_data.uint32 != rhs.m_data.uint32;
case eTypeUInt64: return m_data.uint64 != rhs.m_data.uint64;
#if defined (ENABLE_128_BIT_SUPPORT)
case eTypeUInt128: return m_data.uint128 != rhs.m_data.uint128;
#endif
case eTypeFloat: return m_data.ieee_float != rhs.m_data.ieee_float;
case eTypeDouble: return m_data.ieee_double != rhs.m_data.ieee_double;
case eTypeLongDouble: return m_data.ieee_long_double != rhs.m_data.ieee_long_double;
case eTypeBytes:
if (m_data.buffer.length != rhs.m_data.buffer.length)
{
return true;
}
else
{
uint8_t length = m_data.buffer.length;
if (length > kMaxRegisterByteSize)
length = kMaxRegisterByteSize;
return memcmp (m_data.buffer.bytes, rhs.m_data.buffer.bytes, length) != 0;
}
break;
}
return true;
}

55
lldb/source/Plugins/ABI/MacOSX-arm/ABIMacOSX_arm.cpp
View File

@ -26,6 +26,7 @@
#include "llvm/ADT/Triple.h"
#include "Utility/ARM_DWARF_Registers.h"
#include "Plugins/Process/Utility/ARMDefines.h"
#include <vector>
@ -107,6 +108,9 @@ ABIMacOSX_arm::PrepareTrivialCall (Thread &thread,
return false;
if (arg5_ptr)
{
// Keep the stack 8 byte aligned, not that we need to
sp -= 8;
sp &= ~(8ull-1ull);
reg_value.SetUInt32(*arg5_ptr);
if (reg_ctx->WriteRegisterValueToMemory (reg_info, sp, reg_info->byte_size, reg_value).Fail())
return false;
@ -121,8 +125,26 @@ ABIMacOSX_arm::PrepareTrivialCall (Thread &thread,
}
}
}
// Figure out if our return address is ARM or Thumb. We assume if we don't
// know about an address then it is ARM code.
// Set "lr" to the return address into "lr"
Target *target = &thread.GetProcess().GetTarget();
Address so_addr;
bool ra_is_thumb = false;
if (return_addr & 3)
ra_is_thumb = true;
else if (so_addr.SetLoadAddress (return_addr, target))
ra_is_thumb = so_addr.GetAddressClass() == eAddressClassCodeAlternateISA;
// Set our clear bit zero for the return address if needed. We should never
// need to clear bit zero since the return address will either have bit zero
// or bit one (a thumb instruction on a two byte boundary) already set, or
// it won't and it will need it.
if (ra_is_thumb)
return_addr |= 1u;
// Set "lr" to the return address
if (!reg_ctx->WriteRegisterFromUnsigned (ra_reg_num, return_addr))
return false;
@ -130,10 +152,39 @@ ABIMacOSX_arm::PrepareTrivialCall (Thread &thread,
if (!reg_ctx->WriteRegisterFromUnsigned (sp_reg_num, sp))
return false;
bool pc_is_thumb = false;
// If bit zero or 1 is set, this must be a thumb function, no need to figure
// this out from the symbols.
if (function_addr & 3)
pc_is_thumb = true;
else if (so_addr.SetLoadAddress (function_addr, target))
pc_is_thumb = so_addr.GetAddressClass() == eAddressClassCodeAlternateISA;
const RegisterInfo *cpsr_reg_info = reg_ctx->GetRegisterInfoByName("cpsr");
const uint32_t curr_cpsr = reg_ctx->ReadRegisterAsUnsigned(cpsr_reg_info, 0);
// Make a new CPSR and mask out any Thumb IT (if/then) bits
uint32_t new_cpsr = curr_cpsr & ~MASK_CPSR_IT_MASK;
// If bit zero or 1 is set, this must be thumb...
if (pc_is_thumb)
new_cpsr |= MASK_CPSR_T; // Set T bit in CPSR
else
new_cpsr &= ~MASK_CPSR_T; // Clear T bit in CPSR
if (new_cpsr != curr_cpsr)
{
if (!reg_ctx->WriteRegisterFromUnsigned (cpsr_reg_info, new_cpsr))
return false;
}
function_addr &= ~1u; // clear bit zero since the CPSR will take care of the mode for us
// Set "pc" to the address requested
if (!reg_ctx->WriteRegisterFromUnsigned (pc_reg_num, function_addr))
return false;
return true;
}

4
lldb/source/Plugins/ABI/MacOSX-i386/ABIMacOSX_i386.cpp
View File

@ -111,7 +111,7 @@ ABIMacOSX_i386::PrepareTrivialCall (Thread &thread,
}
// Align the SP
sp &= ~(0xfull); // 16-byte alignment
sp &= ~(16ull-1ull); // 16-byte alignment
if (arg1_ptr)
{
@ -362,7 +362,7 @@ ABIMacOSX_i386::PrepareNormalCall (Thread &thread,
// Align the SP
sp &= ~(0xfull); // 16-byte alignment
sp &= ~(16ull-1ull); // 16-byte alignment
// Write the arguments on the stack

5
lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
View File

@ -1871,8 +1871,11 @@ EmulateInstructionARM::EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPushRegisterOnStack;
RegisterInfo sp_reg;
RegisterInfo dwarf_reg;
GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
context.SetRegisterPlusOffset (sp_reg, addr - sp);
GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rt, dwarf_reg);
context.SetRegisterToRegisterPlusOffset ( dwarf_reg, sp_reg, addr - sp);
if (Rt != 15)
{
uint32_t reg_value = ReadCoreReg(Rt, &success);

3
lldb/source/Plugins/Process/Utility/ARMDefines.h
View File

@ -89,7 +89,8 @@ static inline const char *ARMCondCodeToString(uint32_t CC)
#define CPSR_MODE_SYS 0x1fu
// Masks for CPSR
#define MASK_CPSR_MODE_MASK (0x0000001fu)
#define MASK_CPSR_MODE_MASK (0x0000001fu)
#define MASK_CPSR_IT_MASK (0x0600fc00u)
#define MASK_CPSR_T (1u << CPSR_T_POS)
#define MASK_CPSR_F (1u << CPSR_F_POS)
#define MASK_CPSR_I (1u << CPSR_I_POS)

114
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
View File

@ -507,65 +507,65 @@ GDBRemoteDynamicRegisterInfo::HardcodeARMRegisters()
{ "sp", "r13", 4, 0, eEncodingUint, eFormatHex, { gcc_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, 13, 13 }},
{ "lr", "r14", 4, 0, eEncodingUint, eFormatHex, { gcc_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, 14, 14 }},
{ "pc", "r15", 4, 0, eEncodingUint, eFormatHex, { gcc_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, 15, 15 }},
{ "f0", NULL, 12, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 16, 16 }},
{ "f1", NULL, 12, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 17, 17 }},
{ "f2", NULL, 12, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 18, 18 }},
{ "f3", NULL, 12, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 19, 19 }},
{ "f4", NULL, 12, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 20, 20 }},
{ "f5", NULL, 12, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 21, 21 }},
{ "f6", NULL, 12, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 22, 22 }},
{ "f7", NULL, 12, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 23, 23 }},
{ "fps", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 24, 24 }},
{ "f0", NULL, 12, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 16, 16 }},
{ "f1", NULL, 12, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 17, 17 }},
{ "f2", NULL, 12, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 18, 18 }},
{ "f3", NULL, 12, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 19, 19 }},
{ "f4", NULL, 12, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 20, 20 }},
{ "f5", NULL, 12, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 21, 21 }},
{ "f6", NULL, 12, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 22, 22 }},
{ "f7", NULL, 12, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 23, 23 }},
{ "fps", NULL, 4, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 24, 24 }},
{ "cpsr","flags", 4, 0, eEncodingUint, eFormatHex, { gcc_cpsr, dwarf_cpsr, LLDB_INVALID_REGNUM, 25, 25 }},
{ "s0", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, 26, 26 }},
{ "s1", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, 27, 27 }},
{ "s2", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, 28, 28 }},
{ "s3", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, 29, 29 }},
{ "s4", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, 30, 30 }},
{ "s5", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, 31, 31 }},
{ "s6", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, 32, 32 }},
{ "s7", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, 33, 33 }},
{ "s8", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, 34, 34 }},
{ "s9", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, 35, 35 }},
{ "s10", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, 36, 36 }},
{ "s11", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, 37, 37 }},
{ "s12", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, 38, 38 }},
{ "s13", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, 39, 39 }},
{ "s14", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, 40, 40 }},
{ "s15", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, 41, 41 }},
{ "s16", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, 42, 42 }},
{ "s17", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, 43, 43 }},
{ "s18", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, 44, 44 }},
{ "s19", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, 45, 45 }},
{ "s20", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, 46, 46 }},
{ "s21", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, 47, 47 }},
{ "s22", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, 48, 48 }},
{ "s23", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, 49, 49 }},
{ "s24", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, 50, 50 }},
{ "s25", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, 51, 51 }},
{ "s26", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, 52, 52 }},
{ "s27", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, 53, 53 }},
{ "s28", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, 54, 54 }},
{ "s29", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, 55, 55 }},
{ "s30", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, 56, 56 }},
{ "s31", NULL, 4, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, 57, 57 }},
{ "s0", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, 26, 26 }},
{ "s1", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, 27, 27 }},
{ "s2", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, 28, 28 }},
{ "s3", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, 29, 29 }},
{ "s4", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, 30, 30 }},
{ "s5", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, 31, 31 }},
{ "s6", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, 32, 32 }},
{ "s7", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, 33, 33 }},
{ "s8", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, 34, 34 }},
{ "s9", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, 35, 35 }},
{ "s10", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, 36, 36 }},
{ "s11", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, 37, 37 }},
{ "s12", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, 38, 38 }},
{ "s13", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, 39, 39 }},
{ "s14", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, 40, 40 }},
{ "s15", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, 41, 41 }},
{ "s16", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, 42, 42 }},
{ "s17", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, 43, 43 }},
{ "s18", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, 44, 44 }},
{ "s19", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, 45, 45 }},
{ "s20", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, 46, 46 }},
{ "s21", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, 47, 47 }},
{ "s22", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, 48, 48 }},
{ "s23", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, 49, 49 }},
{ "s24", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, 50, 50 }},
{ "s25", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, 51, 51 }},
{ "s26", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, 52, 52 }},
{ "s27", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, 53, 53 }},
{ "s28", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, 54, 54 }},
{ "s29", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, 55, 55 }},
{ "s30", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, 56, 56 }},
{ "s31", NULL, 4, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, 57, 57 }},
{ "fpscr",NULL, 4, 0, eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 58, 58 }},
{ "d16", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d16, LLDB_INVALID_REGNUM, 59, 59 }},
{ "d17", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d17, LLDB_INVALID_REGNUM, 60, 60 }},
{ "d18", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d18, LLDB_INVALID_REGNUM, 61, 61 }},
{ "d19", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d19, LLDB_INVALID_REGNUM, 62, 62 }},
{ "d20", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d20, LLDB_INVALID_REGNUM, 63, 63 }},
{ "d21", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d21, LLDB_INVALID_REGNUM, 64, 64 }},
{ "d22", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d22, LLDB_INVALID_REGNUM, 65, 65 }},
{ "d23", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d23, LLDB_INVALID_REGNUM, 66, 66 }},
{ "d24", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d24, LLDB_INVALID_REGNUM, 67, 67 }},
{ "d25", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d25, LLDB_INVALID_REGNUM, 68, 68 }},
{ "d26", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d26, LLDB_INVALID_REGNUM, 69, 69 }},
{ "d27", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d27, LLDB_INVALID_REGNUM, 70, 70 }},
{ "d28", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d28, LLDB_INVALID_REGNUM, 71, 71 }},
{ "d29", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d29, LLDB_INVALID_REGNUM, 72, 72 }},
{ "d30", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d30, LLDB_INVALID_REGNUM, 73, 73 }},
{ "d31", NULL, 8, 0, eEncodingIEEE754, eFormatHex, { LLDB_INVALID_REGNUM, dwarf_d31, LLDB_INVALID_REGNUM, 74, 74 }},
{ "d16", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d16, LLDB_INVALID_REGNUM, 59, 59 }},
{ "d17", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d17, LLDB_INVALID_REGNUM, 60, 60 }},
{ "d18", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d18, LLDB_INVALID_REGNUM, 61, 61 }},
{ "d19", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d19, LLDB_INVALID_REGNUM, 62, 62 }},
{ "d20", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d20, LLDB_INVALID_REGNUM, 63, 63 }},
{ "d21", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d21, LLDB_INVALID_REGNUM, 64, 64 }},
{ "d22", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d22, LLDB_INVALID_REGNUM, 65, 65 }},
{ "d23", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d23, LLDB_INVALID_REGNUM, 66, 66 }},
{ "d24", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d24, LLDB_INVALID_REGNUM, 67, 67 }},
{ "d25", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d25, LLDB_INVALID_REGNUM, 68, 68 }},
{ "d26", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d26, LLDB_INVALID_REGNUM, 69, 69 }},
{ "d27", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d27, LLDB_INVALID_REGNUM, 70, 70 }},
{ "d28", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d28, LLDB_INVALID_REGNUM, 71, 71 }},
{ "d29", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d29, LLDB_INVALID_REGNUM, 72, 72 }},
{ "d30", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d30, LLDB_INVALID_REGNUM, 73, 73 }},
{ "d31", NULL, 8, 0, eEncodingIEEE754, eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_d31, LLDB_INVALID_REGNUM, 74, 74 }},
};
static const uint32_t num_registers = sizeof (g_register_infos)/sizeof (RegisterInfo);

69
lldb/source/Target/ThreadPlanTracer.cpp
View File

@ -137,21 +137,13 @@ ThreadPlanAssemblyTracer::TracingStarted ()
RegisterContext *reg_ctx = m_thread.GetRegisterContext().get();
if (m_register_values.size() == 0)
{
for (uint32_t reg_index = 0, num_registers = reg_ctx->GetRegisterCount();
reg_index < num_registers;
++reg_index)
m_register_values.push_back(0);
}
m_register_values.resize (reg_ctx->GetRegisterCount());
}
void
ThreadPlanAssemblyTracer::TracingEnded ()
{
for (uint32_t reg_index = 0, num_registers = m_register_values.size();
reg_index < num_registers;
++reg_index)
m_register_values[reg_index] = 0;
m_register_values.clear();
}
static void
@ -178,17 +170,10 @@ ThreadPlanAssemblyTracer::Log ()
lldb::addr_t pc = reg_ctx->GetPC();
Address pc_addr;
bool addr_valid = false;
StreamString desc;
int desired_width = 0;
addr_valid = m_process.GetTarget().GetSectionLoadList().ResolveLoadAddress (pc, pc_addr);
pc_addr.Dump(&desc, &m_thread, Address::DumpStyleResolvedDescription, Address::DumpStyleModuleWithFileAddress);
desired_width += 64;
PadOutTo(desc, desired_width);
pc_addr.Dump(stream, &m_thread, Address::DumpStyleResolvedDescription, Address::DumpStyleModuleWithFileAddress);
if (m_disassembler)
{
@ -213,18 +198,17 @@ ThreadPlanAssemblyTracer::Log ()
if (instruction_list.GetSize())
{
const bool show_bytes = true;
const bool show_address = true;
Instruction *instruction = instruction_list.GetInstructionAtIndex(0).get();
instruction->Dump (&desc,
instruction->Dump (stream,
max_opcode_byte_size,
false,
false,
show_address,
show_bytes,
NULL,
true);
}
}
desired_width += 32;
PadOutTo(desc, desired_width);
}
if (m_abi && m_intptr_type.GetOpaqueQualType())
@ -244,30 +228,35 @@ ThreadPlanAssemblyTracer::Log ()
{
for (int arg_index = 0; arg_index < num_args; ++arg_index)
{
desc.Printf("arg[%d]=%llx", arg_index, value_list.GetValueAtIndex(arg_index)->GetScalar().ULongLong());
stream->Printf("\n\targ[%d]=%llx", arg_index, value_list.GetValueAtIndex(arg_index)->GetScalar().ULongLong());
if (arg_index + 1 < num_args)
desc.Printf(", ");
stream->PutCString (", ");
}
}
}
desired_width += 20;
PadOutTo(desc, desired_width);
for (uint32_t reg_index = 0, num_registers = reg_ctx->GetRegisterCount();
reg_index < num_registers;
++reg_index)
RegisterValue reg_value;
for (uint32_t reg_num = 0, num_registers = reg_ctx->GetRegisterCount();
reg_num < num_registers;
++reg_num)
{
uint64_t reg_value = reg_ctx->ReadRegisterAsUnsigned(reg_index, 0x0);
if (reg_value != m_register_values[reg_index])
const RegisterInfo *reg_info = reg_ctx->GetRegisterInfoAtIndex(reg_num);
if (reg_ctx->ReadRegister (reg_info, reg_value))
{
desc.Printf ("%s:0x%llx->0x%llx ", reg_ctx->GetRegisterName(reg_index), m_register_values[reg_index], reg_value);
m_register_values[reg_index] = reg_value;
assert (reg_num < m_register_values.size());
if (m_register_values[reg_num].GetType() == RegisterValue::eTypeInvalid ||
reg_value != m_register_values[reg_num])
{
if (reg_value.GetType() != RegisterValue::eTypeInvalid)
{
stream->PutCString ("\n\t");
reg_value.Dump(stream, reg_info, true, false, eFormatDefault);
}
}
m_register_values[reg_num] = reg_value;
}
}
stream->Printf ("Single-step: %s\n", desc.GetString().c_str());
stream->EOL();
}