forked from OSchip/llvm-project
[PhaseOrdering] Add tests for PR44461 and PR48844 (NFC)
In both cases, optimization is prevented because "br X == C || X == C2" is converted into a switch. In one case loop rotation is blocked, in the other vectorization.
This commit is contained in:
Nikita Popov
parent
5c62d66131
commit
cd3d80eace
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -O2 -mattr=avx < %s | FileCheck %s
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; RUN: opt -S -passes='default<O2>' -mattr=avx < %s | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; FIXME: The br -> switch conversion blocks vectorization.
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define dso_local void @test(i32* %start, i32* %end) #0 {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[I11_NOT1:%.*]] = icmp eq i32* [[START:%.*]], [[END:%.*]]
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; CHECK-NEXT: br i1 [[I11_NOT1]], label [[EXIT:%.*]], label [[BB12:%.*]]
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; CHECK: bb12:
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; CHECK-NEXT: [[PTR2:%.*]] = phi i32* [ [[PTR_NEXT:%.*]], [[LATCH:%.*]] ], [ [[START]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[PTR2]], align 4
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; CHECK-NEXT: switch i32 [[VAL]], label [[LATCH]] [
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; CHECK-NEXT: i32 -12, label [[STORE:%.*]]
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; CHECK-NEXT: i32 13, label [[STORE]]
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; CHECK-NEXT: ]
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; CHECK: store:
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; CHECK-NEXT: store i32 42, i32* [[PTR2]], align 4
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; CHECK-NEXT: br label [[LATCH]]
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; CHECK: latch:
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; CHECK-NEXT: [[PTR_NEXT]] = getelementptr inbounds i32, i32* [[PTR2]], i64 1
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; CHECK-NEXT: [[I11_NOT:%.*]] = icmp eq i32* [[PTR_NEXT]], [[END]]
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; CHECK-NEXT: br i1 [[I11_NOT]], label [[EXIT]], label [[BB12]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %header
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header:
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%ptr = phi i32* [ %start, %entry ], [ %ptr.next, %latch ]
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%i11 = icmp ne i32* %ptr, %end
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br i1 %i11, label %bb12, label %exit
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bb12:
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%val = load i32, i32* %ptr, align 4
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%c1 = icmp eq i32 %val, 13
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%c2 = icmp eq i32 %val, -12
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%c3 = or i1 %c1, %c2
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br i1 %c3, label %store, label %latch
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store:
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store i32 42, i32* %ptr, align 4
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br label %latch
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latch:
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%ptr.next = getelementptr inbounds i32, i32* %ptr, i32 1
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br label %header
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exit:
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ret void
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}
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@ -0,0 +1,52 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -O2 < %s | FileCheck %s
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; RUN: opt -S -passes='default<O2>' < %s | FileCheck %s
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; FIXME: The br -> switch conversion blocks loop rotation.
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define i64 @test() {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: start:
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; CHECK-NEXT: br label [[BB10:%.*]]
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; CHECK: bb10:
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; CHECK-NEXT: [[ITER1_SROA_5_0:%.*]] = phi i64 [ 100000, [[START:%.*]] ], [ [[SPEC_SELECT:%.*]], [[BB3_I_I:%.*]] ]
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; CHECK-NEXT: [[ITER1_SROA_9_0:%.*]] = phi i2 [ -2, [[START]] ], [ [[TMP3:%.*]], [[BB3_I_I]] ]
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; CHECK-NEXT: [[COUNT_1:%.*]] = phi i64 [ 0, [[START]] ], [ [[TMP4:%.*]], [[BB3_I_I]] ]
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; CHECK-NEXT: switch i2 [[ITER1_SROA_9_0]], label [[BB12:%.*]] [
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; CHECK-NEXT: i2 -2, label [[BB3_I_I]]
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; CHECK-NEXT: i2 0, label [[BB3_I_I]]
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; CHECK-NEXT: ]
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; CHECK: bb3.i.i:
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[ITER1_SROA_5_0]], 0
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; CHECK-NEXT: [[TMP3]] = zext i1 [[TMP2]] to i2
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; CHECK-NEXT: [[_5_0_I_I_I_I:%.*]] = add i64 [[ITER1_SROA_5_0]], -1
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; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP2]], i64 0, i64 [[_5_0_I_I_I_I]]
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; CHECK-NEXT: [[TMP4]] = add i64 [[COUNT_1]], [[ITER1_SROA_5_0]]
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; CHECK-NEXT: br label [[BB10]]
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; CHECK: bb12:
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; CHECK-NEXT: ret i64 [[COUNT_1]]
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;
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start:
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br label %bb10
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bb10: ; preds = %bb3.i.i, %bb6
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%iter1.sroa.5.0 = phi i64 [ 100000, %start ], [ %spec.select, %bb3.i.i ]
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%iter1.sroa.9.0 = phi i8 [ 2, %start ], [ %tmp3, %bb3.i.i ]
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%count.1 = phi i64 [ 0, %start ], [ %tmp4, %bb3.i.i ]
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%c1 = icmp eq i8 %iter1.sroa.9.0, 2
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%c2 = icmp eq i8 %iter1.sroa.9.0, 0
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%c3 = or i1 %c1, %c2
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br i1 %c3, label %bb3.i.i, label %bb12
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bb3.i.i: ; preds = %bb10, %bb10
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%tmp2 = icmp eq i64 %iter1.sroa.5.0, 0
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%tmp3 = zext i1 %tmp2 to i8
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%_5.0.i.i.i.i = add i64 %iter1.sroa.5.0, -1
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%spec.select = select i1 %tmp2, i64 0, i64 %_5.0.i.i.i.i
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%tmp4 = add i64 %count.1, %iter1.sroa.5.0
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br label %bb10
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bb12: ; preds = %bb10
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ret i64 %count.1
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}
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