From cd2a9ff39788578f419d41f32d046150462696e2 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 24 Jan 2022 07:54:59 -0800 Subject: [PATCH] [RISCV] Select int_riscv_vsll with shift of 1 to vadd.vv. Add might be faster than shift. We can't do this earlier without using a Freeze instruction. This is the intrinsic version of D106689. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D118013 --- .../Target/RISCV/RISCVInstrInfoVPseudos.td | 24 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll | 32 +++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll | 32 +++++++++++++++++++ 3 files changed, 88 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 798f848a50b7..3d4864003b51 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -4543,6 +4543,30 @@ defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors, defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors, uimm5>; +foreach vti = AllIntegerVectors in { + // Emit shift by 1 as an add since it might be faster. + def : Pat<(vti.Vector (int_riscv_vsll (vti.Vector vti.RegClass:$rs1), + (XLenVT 1), VLOpFrag)), + (!cast("PseudoVADD_VV_"#vti.LMul.MX) vti.RegClass:$rs1, + vti.RegClass:$rs1, + GPR:$vl, + vti.Log2SEW)>; + def : Pat<(vti.Vector (int_riscv_vsll_mask (vti.Vector vti.RegClass:$merge), + (vti.Vector vti.RegClass:$rs1), + (XLenVT 1), + (vti.Mask V0), + VLOpFrag, + (XLenVT timm:$policy))), + (!cast("PseudoVADD_VV_"#vti.LMul.MX#"_MASK") + vti.RegClass:$merge, + vti.RegClass:$rs1, + vti.RegClass:$rs1, + (vti.Mask V0), + GPR:$vl, + vti.Log2SEW, + (XLenVT timm:$policy))>; +} + //===----------------------------------------------------------------------===// // 12.7. Vector Narrowing Integer Right Shift Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll index 3f555dba39c5..cd141520ce54 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll @@ -2000,6 +2000,21 @@ entry: ret %a } +define @intrinsic_vsll_1_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_1_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vsll.nxv1i8( + %0, + i32 1, + i32 %1) + + ret %a +} + define @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry @@ -2017,6 +2032,23 @@ entry: ret %a } +define @intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vsll.mask.nxv1i8( + %0, + %1, + i32 1, + %2, + i32 %3, i32 1) + + ret %a +} + define @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll index 8aa798d3b9e6..305f8712b0f4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll @@ -2000,6 +2000,21 @@ entry: ret %a } +define @intrinsic_vsll_1_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_1_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vsll.nxv1i8( + %0, + i64 1, + i64 %1) + + ret %a +} + define @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry @@ -2017,6 +2032,23 @@ entry: ret %a } +define @intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vsll.mask.nxv1i8( + %0, + %1, + i64 1, + %2, + i64 %3, i64 1) + + ret %a +} + define @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry