forked from OSchip/llvm-project
[X86] Remove unneeded code that looks for (and (i8 (X86setcc_c))
I don't believe we use this construct anymore so I don't think we need to look for it.
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@ -43869,28 +43869,10 @@ static SDValue combineFMADDSUB(SDNode *N, SelectionDAG &DAG,
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static SDValue combineZext(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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// (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
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// (and (i32 x86isd::setcc_carry), 1)
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// This eliminates the zext. This transformation is necessary because
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// ISD::SETCC is always legalized to i8.
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SDLoc dl(N);
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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if (N0.getOpcode() == ISD::AND &&
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N0.hasOneUse() &&
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N0.getOperand(0).hasOneUse()) {
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SDValue N00 = N0.getOperand(0);
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if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
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if (!isOneConstant(N0.getOperand(1)))
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return SDValue();
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return DAG.getNode(ISD::AND, dl, VT,
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DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
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N00.getOperand(0), N00.getOperand(1)),
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DAG.getConstant(1, dl, VT));
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}
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}
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if (SDValue NewCMov = combineToExtendCMOV(N, DAG))
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return NewCMov;
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@ -349,13 +349,6 @@ def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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(SETB_C64r)>;
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// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
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// will be eliminated and that the sbb can be extended up to a wider type. When
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// this happens, it is great. However, if we are left with an 8-bit sbb and an
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// and, we might as well just match it as a setb.
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def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
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(SETCCr (i8 2))>;
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// Patterns to give priority when both inputs are zero so that we don't use
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// an immediate for the RHS.
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// TODO: Should we use a 32-bit sbb for 8/16 to push the extract_subreg out?
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