forked from OSchip/llvm-project
[FastISel][AArch64] Fix sign-/zero-extend folding when SelectionDAG is involved.
Sign-/zero-extend folding depended on the load and the integer extend to be both selected by FastISel. This cannot always be garantueed and SelectionDAG might interfer. This commit adds additonal checks to load and integer extend lowering to catch this. Related to rdar://problem/18495928. llvm-svn: 219716
This commit is contained in:
Juergen Ributzka
parent
ca0a38e0ae
commit
cd11a2806b
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@ -150,6 +150,7 @@ private:
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unsigned Alignment);
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bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
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const Value *Cond);
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bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
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// Emit helper routines.
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unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
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@ -178,8 +179,8 @@ private:
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bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
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bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
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bool emitLoad(MVT VT, MVT ResultVT, unsigned &ResultReg, Address Addr,
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bool WantZExt = true, MachineMemOperand *MMO = nullptr);
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unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
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MachineMemOperand *MMO = nullptr);
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bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
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MachineMemOperand *MMO = nullptr);
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unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
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@ -1631,12 +1632,11 @@ unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
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return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
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}
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bool AArch64FastISel::emitLoad(MVT VT, MVT RetVT, unsigned &ResultReg,
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Address Addr, bool WantZExt,
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MachineMemOperand *MMO) {
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unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
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bool WantZExt, MachineMemOperand *MMO) {
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// Simplify this down to something we can handle.
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if (!simplifyAddress(Addr, VT))
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return false;
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return 0;
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unsigned ScaleFactor = getImplicitScaleFactor(VT);
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if (!ScaleFactor)
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@ -1740,13 +1740,20 @@ bool AArch64FastISel::emitLoad(MVT VT, MVT RetVT, unsigned &ResultReg,
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}
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// Create the base instruction, then add the operands.
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ResultReg = createResultReg(RC);
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unsigned ResultReg = createResultReg(RC);
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MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(Opc), ResultReg);
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addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
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// Loading an i1 requires special handling.
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if (VT == MVT::i1) {
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unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
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assert(ANDReg && "Unexpected AND instruction emission failure.");
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ResultReg = ANDReg;
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}
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// For zero-extending loads to 64bit we emit a 32bit load and then convert
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// the w-reg to an x-reg. In the end this is just an noop and will be removed.
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// the 32bit reg to a 64bit reg.
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if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) {
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unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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@ -1756,15 +1763,7 @@ bool AArch64FastISel::emitLoad(MVT VT, MVT RetVT, unsigned &ResultReg,
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.addImm(AArch64::sub_32);
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ResultReg = Reg64;
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}
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// Loading an i1 requires special handling.
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if (VT == MVT::i1) {
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unsigned ANDReg = emitAnd_ri(IsRet64Bit ? MVT::i64 : MVT::i32, ResultReg,
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/*IsKill=*/true, 1);
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assert(ANDReg && "Unexpected AND instruction emission failure.");
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ResultReg = ANDReg;
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}
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return true;
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return ResultReg;
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}
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bool AArch64FastISel::selectAddSub(const Instruction *I) {
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@ -1836,24 +1835,82 @@ bool AArch64FastISel::selectLoad(const Instruction *I) {
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if (!computeAddress(I->getOperand(0), Addr, I->getType()))
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return false;
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// Fold the following sign-/zero-extend into the load instruction.
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bool WantZExt = true;
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MVT RetVT = VT;
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const Value *IntExtVal = nullptr;
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if (I->hasOneUse()) {
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if (const auto *ZE = dyn_cast<ZExtInst>(I->use_begin()->getUser())) {
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if (!isTypeSupported(ZE->getType(), RetVT, /*IsVectorAllowed=*/false))
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if (isTypeSupported(ZE->getType(), RetVT))
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IntExtVal = ZE;
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else
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RetVT = VT;
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} else if (const auto *SE = dyn_cast<SExtInst>(I->use_begin()->getUser())) {
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if (!isTypeSupported(SE->getType(), RetVT, /*IsVectorAllowed=*/false))
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if (isTypeSupported(SE->getType(), RetVT))
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IntExtVal = SE;
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else
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RetVT = VT;
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WantZExt = false;
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}
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}
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unsigned ResultReg;
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if (!emitLoad(VT, RetVT, ResultReg, Addr, WantZExt,
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createMachineMemOperandFor(I)))
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unsigned ResultReg =
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emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I));
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if (!ResultReg)
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return false;
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// There are a few different cases we have to handle, because the load or the
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// sign-/zero-extend might not be selected by FastISel if we fall-back to
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// SelectionDAG. There is also an ordering issue when both instructions are in
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// different basic blocks.
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// 1.) The load instruction is selected by FastISel, but the integer extend
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// not. This usually happens when the integer extend is in a different
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// basic block and SelectionDAG took over for that basic block.
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// 2.) The load instruction is selected before the integer extend. This only
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// happens when the integer extend is in a different basic block.
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// 3.) The load instruction is selected by SelectionDAG and the integer extend
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// by FastISel. This happens if there are instructions between the load
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// and the integer extend that couldn't be selected by FastISel.
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if (IntExtVal) {
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// The integer extend hasn't been emitted yet. FastISel or SelectionDAG
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// could select it. Emit a copy to subreg if necessary. FastISel will remove
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// it when it selects the integer extend.
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unsigned Reg = lookUpRegForValue(IntExtVal);
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if (!Reg) {
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if (RetVT == MVT::i64 && VT <= MVT::i32) {
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if (WantZExt) {
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// Delete the last emitted instruction from emitLoad (SUBREG_TO_REG).
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std::prev(FuncInfo.InsertPt)->eraseFromParent();
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ResultReg = std::prev(FuncInfo.InsertPt)->getOperand(0).getReg();
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} else
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ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg,
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/*IsKill=*/true,
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AArch64::sub_32);
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}
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updateValueMap(I, ResultReg);
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return true;
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}
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// The integer extend has already been emitted - delete all the instructions
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// that have been emitted by the integer extend lowering code and use the
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// result from the load instruction directly.
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while (Reg) {
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auto *MI = MRI.getUniqueVRegDef(Reg);
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if (!MI)
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break;
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Reg = 0;
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for (auto &Opnd : MI->uses()) {
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if (Opnd.isReg()) {
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Reg = Opnd.getReg();
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break;
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}
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}
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MI->eraseFromParent();
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}
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updateValueMap(IntExtVal, ResultReg);
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return true;
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}
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updateValueMap(I, ResultReg);
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return true;
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}
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@ -2104,13 +2161,12 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
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return false;
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bool SrcIsKill = hasTrivialKill(LHS);
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if (BW == 64 && !Is64Bit) {
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if (BW == 64 && !Is64Bit)
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SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
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AArch64::sub_32);
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SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
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}
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// Emit the combined compare and branch instruction.
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SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
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MachineInstrBuilder MIB =
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
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.addReg(SrcReg, getKillRegState(SrcIsKill));
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@ -2975,14 +3031,11 @@ bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,
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}
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}
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bool RV;
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unsigned ResultReg;
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RV = emitLoad(VT, VT, ResultReg, Src);
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if (!RV)
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unsigned ResultReg = emitLoad(VT, VT, Src);
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if (!ResultReg)
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return false;
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RV = emitStore(VT, ResultReg, Dest);
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if (!RV)
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if (!emitStore(VT, ResultReg, Dest))
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return false;
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int64_t Size = VT.getSizeInBits() / 8;
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@ -3986,6 +4039,107 @@ unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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return fastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
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}
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static bool isZExtLoad(const MachineInstr *LI) {
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switch (LI->getOpcode()) {
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default:
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return false;
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case AArch64::LDURBBi:
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case AArch64::LDURHHi:
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case AArch64::LDURWi:
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case AArch64::LDRBBui:
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case AArch64::LDRHHui:
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case AArch64::LDRWui:
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case AArch64::LDRBBroX:
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case AArch64::LDRHHroX:
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case AArch64::LDRWroX:
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case AArch64::LDRBBroW:
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case AArch64::LDRHHroW:
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case AArch64::LDRWroW:
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return true;
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}
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}
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static bool isSExtLoad(const MachineInstr *LI) {
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switch (LI->getOpcode()) {
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default:
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return false;
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case AArch64::LDURSBWi:
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case AArch64::LDURSHWi:
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case AArch64::LDURSBXi:
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case AArch64::LDURSHXi:
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case AArch64::LDURSWi:
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case AArch64::LDRSBWui:
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case AArch64::LDRSHWui:
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case AArch64::LDRSBXui:
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case AArch64::LDRSHXui:
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case AArch64::LDRSWui:
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case AArch64::LDRSBWroX:
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case AArch64::LDRSHWroX:
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case AArch64::LDRSBXroX:
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case AArch64::LDRSHXroX:
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case AArch64::LDRSWroX:
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case AArch64::LDRSBWroW:
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case AArch64::LDRSHWroW:
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case AArch64::LDRSBXroW:
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case AArch64::LDRSHXroW:
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case AArch64::LDRSWroW:
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return true;
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}
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}
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bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT,
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MVT SrcVT) {
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const auto *LI = dyn_cast<LoadInst>(I->getOperand(0));
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if (!LI || !LI->hasOneUse())
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return false;
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// Check if the load instruction has already been selected.
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unsigned Reg = lookUpRegForValue(LI);
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if (!Reg)
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return false;
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MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
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if (!MI)
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return false;
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// Check if the correct load instruction has been emitted - SelectionDAG might
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// have emitted a zero-extending load, but we need a sign-extending load.
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bool IsZExt = isa<ZExtInst>(I);
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const auto *LoadMI = MI;
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if (LoadMI->getOpcode() == TargetOpcode::COPY &&
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LoadMI->getOperand(1).getSubReg() == AArch64::sub_32) {
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unsigned LoadReg = MI->getOperand(1).getReg();
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LoadMI = MRI.getUniqueVRegDef(LoadReg);
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assert(LoadMI && "Expected valid instruction");
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}
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if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI)))
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return false;
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// Nothing to be done.
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if (RetVT != MVT::i64 || SrcVT > MVT::i32) {
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updateValueMap(I, Reg);
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return true;
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}
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if (IsZExt) {
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unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBREG_TO_REG), Reg64)
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.addImm(0)
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.addReg(Reg, getKillRegState(true))
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.addImm(AArch64::sub_32);
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Reg = Reg64;
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} else {
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assert((MI->getOpcode() == TargetOpcode::COPY &&
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MI->getOperand(1).getSubReg() == AArch64::sub_32) &&
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"Expected copy instruction");
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Reg = MI->getOperand(1).getReg();
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MI->eraseFromParent();
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}
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updateValueMap(I, Reg);
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return true;
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}
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bool AArch64FastISel::selectIntExt(const Instruction *I) {
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assert((isa<ZExtInst>(I) || isa<SExtInst>(I)) &&
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"Unexpected integer extend instruction.");
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@ -3997,19 +4151,16 @@ bool AArch64FastISel::selectIntExt(const Instruction *I) {
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if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))
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return false;
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// Try to optimize already sign-/zero-extended values from load instructions.
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if (optimizeIntExtLoad(I, RetVT, SrcVT))
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return true;
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unsigned SrcReg = getRegForValue(I->getOperand(0));
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if (!SrcReg)
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return false;
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bool SrcIsKill = hasTrivialKill(I->getOperand(0));
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// The load instruction selection code handles the sign-/zero-extension.
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if (const auto *LI = dyn_cast<LoadInst>(I->getOperand(0))) {
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if (LI->hasOneUse()) {
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updateValueMap(I, SrcReg);
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return true;
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}
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}
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// Try to optimize already sign-/zero-extended values from function arguments.
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bool IsZExt = isa<ZExtInst>(I);
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if (const auto *Arg = dyn_cast<Argument>(I->getOperand(0))) {
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if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
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@ -0,0 +1,439 @@
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s
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;
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; Test folding of the sign-/zero-extend into the load instruction.
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;
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; Unscaled
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define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i8_to_i32
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; CHECK: ldurb w0, [x0, #-8]
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; CHECK-NOT: uxtb
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8* %2
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br label %bb2
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bb2:
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%4 = zext i8 %3 to i32
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ret i32 %4
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}
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define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i16_to_i32
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; CHECK: ldurh w0, [x0, #-8]
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; CHECK-NOT: uxth
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16* %2
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br label %bb2
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bb2:
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%4 = zext i16 %3 to i32
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ret i32 %4
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}
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define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i8_to_i64
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; CHECK: ldurb w0, [x0, #-8]
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; CHECK-NOT: uxtb
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8* %2
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br label %bb2
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bb2:
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%4 = zext i8 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i16_to_i64
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; CHECK: ldurh w0, [x0, #-8]
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; CHECK-NOT: uxth
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16* %2
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br label %bb2
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bb2:
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%4 = zext i16 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i32_to_i64
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; CHECK: ldur w0, [x0, #-8]
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; CHECK-NOT: uxtw
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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br label %bb2
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bb2:
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%4 = zext i32 %3 to i64
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ret i64 %4
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}
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define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i8_to_i32
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; CHECK: ldursb w0, [x0, #-8]
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; CHECK-NOT: sxtb
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%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i8 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i16_to_i32
|
||||
; CHECK: ldursh w0, [x0, #-8]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i16 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i8_to_i64
|
||||
; CHECK: ldursb x0, [x0, #-8]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i8 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i16_to_i64
|
||||
; CHECK: ldursh x0, [x0, #-8]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i16 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i32_to_i64
|
||||
; CHECK: ldursw x0, [x0, #-8]
|
||||
; CHECK-NOT: sxtw
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i32 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
; Register
|
||||
define i32 @load_register_zext_i8_to_i32(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i8_to_i32
|
||||
; CHECK: ldrb w0, [x0, x1]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = zext i8 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_register_zext_i16_to_i32(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i16_to_i32
|
||||
; CHECK: ldrh w0, [x0, x1]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = zext i16 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_zext_i8_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i8_to_i64
|
||||
; CHECK: ldrb w0, [x0, x1]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = zext i8 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_zext_i16_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i16_to_i64
|
||||
; CHECK: ldrh w0, [x0, x1]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = zext i16 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_zext_i32_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i32_to_i64
|
||||
; CHECK: ldr w0, [x0, x1]
|
||||
; CHECK-NOT: uxtw
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = zext i32 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i32 @load_register_sext_i8_to_i32(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i8_to_i32
|
||||
; CHECK: ldrsb w0, [x0, x1]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i8 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_register_sext_i16_to_i32(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i16_to_i32
|
||||
; CHECK: ldrsh w0, [x0, x1]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i16 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_sext_i8_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i8_to_i64
|
||||
; CHECK: ldrsb x0, [x0, x1]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i8 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_sext_i16_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i16_to_i64
|
||||
; CHECK: ldrsh x0, [x0, x1]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i16 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_sext_i32_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i32_to_i64
|
||||
; CHECK: ldrsw x0, [x0, x1]
|
||||
; CHECK-NOT: sxtw
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%4 = sext i32 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
; Extend
|
||||
define i32 @load_extend_zext_i8_to_i32(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i8_to_i32
|
||||
; CHECK: ldrb w0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i8*
|
||||
%4 = load i8* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = zext i8 %4 to i32
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @load_extend_zext_i16_to_i32(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i16_to_i32
|
||||
; CHECK: ldrh w0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i16*
|
||||
%4 = load i16* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = zext i16 %4 to i32
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_zext_i8_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i8_to_i64
|
||||
; CHECK: ldrb w0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i8*
|
||||
%4 = load i8* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = zext i8 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_zext_i16_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i16_to_i64
|
||||
; CHECK: ldrh w0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i16*
|
||||
%4 = load i16* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = zext i16 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_zext_i32_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i32_to_i64
|
||||
; CHECK: ldr w0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: uxtw
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i32*
|
||||
%4 = load i32* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = zext i32 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i32 @load_extend_sext_i8_to_i32(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i8_to_i32
|
||||
; CHECK: ldrsb w0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i8*
|
||||
%4 = load i8* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = sext i8 %4 to i32
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @load_extend_sext_i16_to_i32(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i16_to_i32
|
||||
; CHECK: ldrsh w0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i16*
|
||||
%4 = load i16* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = sext i16 %4 to i32
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_sext_i8_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i8_to_i64
|
||||
; CHECK: ldrsb x0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i8*
|
||||
%4 = load i8* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = sext i8 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_sext_i16_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i16_to_i64
|
||||
; CHECK: ldrsh x0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i16*
|
||||
%4 = load i16* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = sext i16 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_sext_i32_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i32_to_i64
|
||||
; CHECK: ldrsw x0, [x0, w1, sxtw]
|
||||
; CHECK-NOT: sxtw
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i32*
|
||||
%4 = load i32* %3
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%5 = sext i32 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
;
|
||||
; Test folding of the sign-/zero-extend into the load instruction.
|
||||
;
|
||||
|
||||
; Unscaled
|
||||
define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i8_to_i32
|
||||
; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
|
||||
; CHECK: uxtb w0, [[REG]]
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i8 addrspace(256)*
|
||||
%3 = load i8 addrspace(256)* %2
|
||||
%4 = zext i8 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i16_to_i32
|
||||
; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
|
||||
; CHECK: uxth w0, [[REG]]
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i16 addrspace(256)*
|
||||
%3 = load i16 addrspace(256)* %2
|
||||
%4 = zext i16 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i8_to_i64
|
||||
; CHECK: ldurb w[[REG:[0-9]+]], [x0, #-8]
|
||||
; CHECK: ubfx x0, x[[REG]], #0, #8
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i8 addrspace(256)*
|
||||
%3 = load i8 addrspace(256)* %2
|
||||
%4 = zext i8 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i16_to_i64
|
||||
; CHECK: ldurh w[[REG:[0-9]+]], [x0, #-8]
|
||||
; CHECK: ubfx x0, x[[REG]], #0, #16
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i16 addrspace(256)*
|
||||
%3 = load i16 addrspace(256)* %2
|
||||
%4 = zext i16 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i32_to_i64
|
||||
; CHECK: ldur w[[REG:[0-9]+]], [x0, #-8]
|
||||
; CHECK: ubfx x0, x[[REG]], #0, #32
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i32 addrspace(256)*
|
||||
%3 = load i32 addrspace(256)* %2
|
||||
%4 = zext i32 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i8_to_i32
|
||||
; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
|
||||
; CHECK: sxtb w0, [[REG]]
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i8 addrspace(256)*
|
||||
%3 = load i8 addrspace(256)* %2
|
||||
%4 = sext i8 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i16_to_i32
|
||||
; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
|
||||
; CHECK: sxth w0, [[REG]]
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i16 addrspace(256)*
|
||||
%3 = load i16 addrspace(256)* %2
|
||||
%4 = sext i16 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i8_to_i64
|
||||
; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
|
||||
; CHECK: sxtb x0, [[REG]]
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i8 addrspace(256)*
|
||||
%3 = load i8 addrspace(256)* %2
|
||||
%4 = sext i8 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i16_to_i64
|
||||
; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
|
||||
; CHECK: sxth x0, [[REG]]
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i16 addrspace(256)*
|
||||
%3 = load i16 addrspace(256)* %2
|
||||
%4 = sext i16 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i32_to_i64
|
||||
; CHECK: ldur [[REG:w[0-9]+]], [x0, #-8]
|
||||
; CHECK: sxtw x0, [[REG]]
|
||||
%1 = sub i64 %a, 8
|
||||
%2 = inttoptr i64 %1 to i32 addrspace(256)*
|
||||
%3 = load i32 addrspace(256)* %2
|
||||
%4 = sext i32 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue