forked from OSchip/llvm-project
Split ppc dwarf regnums into ppc64 and ppc32 flavours.
llvm-svn: 132315
This commit is contained in:
Rafael Espindola
parent
ddffa0e160
commit
cd0d2fd21f
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@ -686,9 +686,20 @@ unsigned PPCRegisterInfo::getEHHandlerRegister() const {
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return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
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}
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/// DWARFFlavour - Flavour of dwarf regnumbers
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///
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namespace DWARFFlavour {
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enum {
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PPC64 = 0, PPC32 = 1
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};
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}
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int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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// FIXME: Most probably dwarf numbers differs for Linux and Darwin
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return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
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unsigned Flavour = Subtarget.isPPC64() ?
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DWARFFlavour::PPC64 : DWARFFlavour::PPC32;
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return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour);
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}
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#include "PPCGenRegisterInfo.inc"
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@ -65,140 +65,140 @@ class CRBIT<bits<5> num, string n> : PPCReg<n> {
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// General-purpose registers
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def R0 : GPR< 0, "r0">, DwarfRegNum<[0]>;
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def R1 : GPR< 1, "r1">, DwarfRegNum<[1]>;
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def R2 : GPR< 2, "r2">, DwarfRegNum<[2]>;
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def R3 : GPR< 3, "r3">, DwarfRegNum<[3]>;
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def R4 : GPR< 4, "r4">, DwarfRegNum<[4]>;
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def R5 : GPR< 5, "r5">, DwarfRegNum<[5]>;
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def R6 : GPR< 6, "r6">, DwarfRegNum<[6]>;
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def R7 : GPR< 7, "r7">, DwarfRegNum<[7]>;
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def R8 : GPR< 8, "r8">, DwarfRegNum<[8]>;
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def R9 : GPR< 9, "r9">, DwarfRegNum<[9]>;
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def R10 : GPR<10, "r10">, DwarfRegNum<[10]>;
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def R11 : GPR<11, "r11">, DwarfRegNum<[11]>;
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def R12 : GPR<12, "r12">, DwarfRegNum<[12]>;
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def R13 : GPR<13, "r13">, DwarfRegNum<[13]>;
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def R14 : GPR<14, "r14">, DwarfRegNum<[14]>;
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def R15 : GPR<15, "r15">, DwarfRegNum<[15]>;
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def R16 : GPR<16, "r16">, DwarfRegNum<[16]>;
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def R17 : GPR<17, "r17">, DwarfRegNum<[17]>;
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def R18 : GPR<18, "r18">, DwarfRegNum<[18]>;
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def R19 : GPR<19, "r19">, DwarfRegNum<[19]>;
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def R20 : GPR<20, "r20">, DwarfRegNum<[20]>;
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def R21 : GPR<21, "r21">, DwarfRegNum<[21]>;
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def R22 : GPR<22, "r22">, DwarfRegNum<[22]>;
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def R23 : GPR<23, "r23">, DwarfRegNum<[23]>;
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def R24 : GPR<24, "r24">, DwarfRegNum<[24]>;
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def R25 : GPR<25, "r25">, DwarfRegNum<[25]>;
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def R26 : GPR<26, "r26">, DwarfRegNum<[26]>;
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def R27 : GPR<27, "r27">, DwarfRegNum<[27]>;
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def R28 : GPR<28, "r28">, DwarfRegNum<[28]>;
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def R29 : GPR<29, "r29">, DwarfRegNum<[29]>;
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def R30 : GPR<30, "r30">, DwarfRegNum<[30]>;
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def R31 : GPR<31, "r31">, DwarfRegNum<[31]>;
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def R0 : GPR< 0, "r0">, DwarfRegNum<[-2, 0]>;
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def R1 : GPR< 1, "r1">, DwarfRegNum<[-2, 1]>;
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def R2 : GPR< 2, "r2">, DwarfRegNum<[-2, 2]>;
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def R3 : GPR< 3, "r3">, DwarfRegNum<[-2, 3]>;
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def R4 : GPR< 4, "r4">, DwarfRegNum<[-2, 4]>;
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def R5 : GPR< 5, "r5">, DwarfRegNum<[-2, 5]>;
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def R6 : GPR< 6, "r6">, DwarfRegNum<[-2, 6]>;
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def R7 : GPR< 7, "r7">, DwarfRegNum<[-2, 7]>;
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def R8 : GPR< 8, "r8">, DwarfRegNum<[-2, 8]>;
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def R9 : GPR< 9, "r9">, DwarfRegNum<[-2, 9]>;
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def R10 : GPR<10, "r10">, DwarfRegNum<[-2, 10]>;
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def R11 : GPR<11, "r11">, DwarfRegNum<[-2, 11]>;
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def R12 : GPR<12, "r12">, DwarfRegNum<[-2, 12]>;
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def R13 : GPR<13, "r13">, DwarfRegNum<[-2, 13]>;
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def R14 : GPR<14, "r14">, DwarfRegNum<[-2, 14]>;
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def R15 : GPR<15, "r15">, DwarfRegNum<[-2, 15]>;
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def R16 : GPR<16, "r16">, DwarfRegNum<[-2, 16]>;
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def R17 : GPR<17, "r17">, DwarfRegNum<[-2, 17]>;
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def R18 : GPR<18, "r18">, DwarfRegNum<[-2, 18]>;
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def R19 : GPR<19, "r19">, DwarfRegNum<[-2, 19]>;
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def R20 : GPR<20, "r20">, DwarfRegNum<[-2, 20]>;
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def R21 : GPR<21, "r21">, DwarfRegNum<[-2, 21]>;
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def R22 : GPR<22, "r22">, DwarfRegNum<[-2, 22]>;
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def R23 : GPR<23, "r23">, DwarfRegNum<[-2, 23]>;
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def R24 : GPR<24, "r24">, DwarfRegNum<[-2, 24]>;
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def R25 : GPR<25, "r25">, DwarfRegNum<[-2, 25]>;
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def R26 : GPR<26, "r26">, DwarfRegNum<[-2, 26]>;
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def R27 : GPR<27, "r27">, DwarfRegNum<[-2, 27]>;
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def R28 : GPR<28, "r28">, DwarfRegNum<[-2, 28]>;
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def R29 : GPR<29, "r29">, DwarfRegNum<[-2, 29]>;
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def R30 : GPR<30, "r30">, DwarfRegNum<[-2, 30]>;
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def R31 : GPR<31, "r31">, DwarfRegNum<[-2, 31]>;
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// 64-bit General-purpose registers
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def X0 : GP8< R0, "r0">, DwarfRegNum<[0]>;
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def X1 : GP8< R1, "r1">, DwarfRegNum<[1]>;
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def X2 : GP8< R2, "r2">, DwarfRegNum<[2]>;
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def X3 : GP8< R3, "r3">, DwarfRegNum<[3]>;
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def X4 : GP8< R4, "r4">, DwarfRegNum<[4]>;
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def X5 : GP8< R5, "r5">, DwarfRegNum<[5]>;
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def X6 : GP8< R6, "r6">, DwarfRegNum<[6]>;
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def X7 : GP8< R7, "r7">, DwarfRegNum<[7]>;
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def X8 : GP8< R8, "r8">, DwarfRegNum<[8]>;
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def X9 : GP8< R9, "r9">, DwarfRegNum<[9]>;
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def X10 : GP8<R10, "r10">, DwarfRegNum<[10]>;
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def X11 : GP8<R11, "r11">, DwarfRegNum<[11]>;
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def X12 : GP8<R12, "r12">, DwarfRegNum<[12]>;
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def X13 : GP8<R13, "r13">, DwarfRegNum<[13]>;
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def X14 : GP8<R14, "r14">, DwarfRegNum<[14]>;
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def X15 : GP8<R15, "r15">, DwarfRegNum<[15]>;
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def X16 : GP8<R16, "r16">, DwarfRegNum<[16]>;
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def X17 : GP8<R17, "r17">, DwarfRegNum<[17]>;
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def X18 : GP8<R18, "r18">, DwarfRegNum<[18]>;
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def X19 : GP8<R19, "r19">, DwarfRegNum<[19]>;
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def X20 : GP8<R20, "r20">, DwarfRegNum<[20]>;
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def X21 : GP8<R21, "r21">, DwarfRegNum<[21]>;
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def X22 : GP8<R22, "r22">, DwarfRegNum<[22]>;
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def X23 : GP8<R23, "r23">, DwarfRegNum<[23]>;
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def X24 : GP8<R24, "r24">, DwarfRegNum<[24]>;
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def X25 : GP8<R25, "r25">, DwarfRegNum<[25]>;
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def X26 : GP8<R26, "r26">, DwarfRegNum<[26]>;
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def X27 : GP8<R27, "r27">, DwarfRegNum<[27]>;
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def X28 : GP8<R28, "r28">, DwarfRegNum<[28]>;
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def X29 : GP8<R29, "r29">, DwarfRegNum<[29]>;
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def X30 : GP8<R30, "r30">, DwarfRegNum<[30]>;
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def X31 : GP8<R31, "r31">, DwarfRegNum<[31]>;
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def X0 : GP8< R0, "r0">, DwarfRegNum<[0, -2]>;
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def X1 : GP8< R1, "r1">, DwarfRegNum<[1, -2]>;
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def X2 : GP8< R2, "r2">, DwarfRegNum<[2, -2]>;
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def X3 : GP8< R3, "r3">, DwarfRegNum<[3, -2]>;
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def X4 : GP8< R4, "r4">, DwarfRegNum<[4, -2]>;
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def X5 : GP8< R5, "r5">, DwarfRegNum<[5, -2]>;
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def X6 : GP8< R6, "r6">, DwarfRegNum<[6, -2]>;
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def X7 : GP8< R7, "r7">, DwarfRegNum<[7, -2]>;
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def X8 : GP8< R8, "r8">, DwarfRegNum<[8, -2]>;
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def X9 : GP8< R9, "r9">, DwarfRegNum<[9, -2]>;
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def X10 : GP8<R10, "r10">, DwarfRegNum<[10, -2]>;
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def X11 : GP8<R11, "r11">, DwarfRegNum<[11, -2]>;
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def X12 : GP8<R12, "r12">, DwarfRegNum<[12, -2]>;
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def X13 : GP8<R13, "r13">, DwarfRegNum<[13, -2]>;
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def X14 : GP8<R14, "r14">, DwarfRegNum<[14, -2]>;
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def X15 : GP8<R15, "r15">, DwarfRegNum<[15, -2]>;
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def X16 : GP8<R16, "r16">, DwarfRegNum<[16, -2]>;
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def X17 : GP8<R17, "r17">, DwarfRegNum<[17, -2]>;
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def X18 : GP8<R18, "r18">, DwarfRegNum<[18, -2]>;
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def X19 : GP8<R19, "r19">, DwarfRegNum<[19, -2]>;
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def X20 : GP8<R20, "r20">, DwarfRegNum<[20, -2]>;
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def X21 : GP8<R21, "r21">, DwarfRegNum<[21, -2]>;
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def X22 : GP8<R22, "r22">, DwarfRegNum<[22, -2]>;
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def X23 : GP8<R23, "r23">, DwarfRegNum<[23, -2]>;
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def X24 : GP8<R24, "r24">, DwarfRegNum<[24, -2]>;
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def X25 : GP8<R25, "r25">, DwarfRegNum<[25, -2]>;
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def X26 : GP8<R26, "r26">, DwarfRegNum<[26, -2]>;
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def X27 : GP8<R27, "r27">, DwarfRegNum<[27, -2]>;
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def X28 : GP8<R28, "r28">, DwarfRegNum<[28, -2]>;
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def X29 : GP8<R29, "r29">, DwarfRegNum<[29, -2]>;
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def X30 : GP8<R30, "r30">, DwarfRegNum<[30, -2]>;
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def X31 : GP8<R31, "r31">, DwarfRegNum<[31, -2]>;
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// Floating-point registers
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def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>;
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def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>;
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def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>;
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def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>;
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def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>;
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def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>;
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def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>;
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def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>;
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def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>;
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def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>;
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def F10 : FPR<10, "f10">, DwarfRegNum<[42]>;
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def F11 : FPR<11, "f11">, DwarfRegNum<[43]>;
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def F12 : FPR<12, "f12">, DwarfRegNum<[44]>;
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def F13 : FPR<13, "f13">, DwarfRegNum<[45]>;
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def F14 : FPR<14, "f14">, DwarfRegNum<[46]>;
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def F15 : FPR<15, "f15">, DwarfRegNum<[47]>;
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def F16 : FPR<16, "f16">, DwarfRegNum<[48]>;
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def F17 : FPR<17, "f17">, DwarfRegNum<[49]>;
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def F18 : FPR<18, "f18">, DwarfRegNum<[50]>;
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def F19 : FPR<19, "f19">, DwarfRegNum<[51]>;
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def F20 : FPR<20, "f20">, DwarfRegNum<[52]>;
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def F21 : FPR<21, "f21">, DwarfRegNum<[53]>;
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def F22 : FPR<22, "f22">, DwarfRegNum<[54]>;
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def F23 : FPR<23, "f23">, DwarfRegNum<[55]>;
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def F24 : FPR<24, "f24">, DwarfRegNum<[56]>;
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def F25 : FPR<25, "f25">, DwarfRegNum<[57]>;
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def F26 : FPR<26, "f26">, DwarfRegNum<[58]>;
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def F27 : FPR<27, "f27">, DwarfRegNum<[59]>;
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def F28 : FPR<28, "f28">, DwarfRegNum<[60]>;
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def F29 : FPR<29, "f29">, DwarfRegNum<[61]>;
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def F30 : FPR<30, "f30">, DwarfRegNum<[62]>;
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def F31 : FPR<31, "f31">, DwarfRegNum<[63]>;
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def F0 : FPR< 0, "f0">, DwarfRegNum<[32, 32]>;
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def F1 : FPR< 1, "f1">, DwarfRegNum<[33, 33]>;
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def F2 : FPR< 2, "f2">, DwarfRegNum<[34, 34]>;
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def F3 : FPR< 3, "f3">, DwarfRegNum<[35, 35]>;
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def F4 : FPR< 4, "f4">, DwarfRegNum<[36, 36]>;
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def F5 : FPR< 5, "f5">, DwarfRegNum<[37, 37]>;
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def F6 : FPR< 6, "f6">, DwarfRegNum<[38, 38]>;
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def F7 : FPR< 7, "f7">, DwarfRegNum<[39, 39]>;
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def F8 : FPR< 8, "f8">, DwarfRegNum<[40, 40]>;
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def F9 : FPR< 9, "f9">, DwarfRegNum<[41, 41]>;
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def F10 : FPR<10, "f10">, DwarfRegNum<[42, 42]>;
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def F11 : FPR<11, "f11">, DwarfRegNum<[43, 43]>;
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def F12 : FPR<12, "f12">, DwarfRegNum<[44, 44]>;
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def F13 : FPR<13, "f13">, DwarfRegNum<[45, 45]>;
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def F14 : FPR<14, "f14">, DwarfRegNum<[46, 46]>;
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def F15 : FPR<15, "f15">, DwarfRegNum<[47, 47]>;
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def F16 : FPR<16, "f16">, DwarfRegNum<[48, 48]>;
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def F17 : FPR<17, "f17">, DwarfRegNum<[49, 49]>;
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def F18 : FPR<18, "f18">, DwarfRegNum<[50, 50]>;
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def F19 : FPR<19, "f19">, DwarfRegNum<[51, 51]>;
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def F20 : FPR<20, "f20">, DwarfRegNum<[52, 52]>;
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def F21 : FPR<21, "f21">, DwarfRegNum<[53, 53]>;
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def F22 : FPR<22, "f22">, DwarfRegNum<[54, 54]>;
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def F23 : FPR<23, "f23">, DwarfRegNum<[55, 55]>;
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def F24 : FPR<24, "f24">, DwarfRegNum<[56, 56]>;
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def F25 : FPR<25, "f25">, DwarfRegNum<[57, 57]>;
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def F26 : FPR<26, "f26">, DwarfRegNum<[58, 58]>;
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def F27 : FPR<27, "f27">, DwarfRegNum<[59, 59]>;
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def F28 : FPR<28, "f28">, DwarfRegNum<[60, 60]>;
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def F29 : FPR<29, "f29">, DwarfRegNum<[61, 61]>;
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def F30 : FPR<30, "f30">, DwarfRegNum<[62, 62]>;
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def F31 : FPR<31, "f31">, DwarfRegNum<[63, 63]>;
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// Vector registers
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def V0 : VR< 0, "v0">, DwarfRegNum<[77]>;
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def V1 : VR< 1, "v1">, DwarfRegNum<[78]>;
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def V2 : VR< 2, "v2">, DwarfRegNum<[79]>;
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def V3 : VR< 3, "v3">, DwarfRegNum<[80]>;
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def V4 : VR< 4, "v4">, DwarfRegNum<[81]>;
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def V5 : VR< 5, "v5">, DwarfRegNum<[82]>;
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def V6 : VR< 6, "v6">, DwarfRegNum<[83]>;
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def V7 : VR< 7, "v7">, DwarfRegNum<[84]>;
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def V8 : VR< 8, "v8">, DwarfRegNum<[85]>;
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def V9 : VR< 9, "v9">, DwarfRegNum<[86]>;
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def V10 : VR<10, "v10">, DwarfRegNum<[87]>;
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def V11 : VR<11, "v11">, DwarfRegNum<[88]>;
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def V12 : VR<12, "v12">, DwarfRegNum<[89]>;
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def V13 : VR<13, "v13">, DwarfRegNum<[90]>;
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def V14 : VR<14, "v14">, DwarfRegNum<[91]>;
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def V15 : VR<15, "v15">, DwarfRegNum<[92]>;
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def V16 : VR<16, "v16">, DwarfRegNum<[93]>;
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def V17 : VR<17, "v17">, DwarfRegNum<[94]>;
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def V18 : VR<18, "v18">, DwarfRegNum<[95]>;
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def V19 : VR<19, "v19">, DwarfRegNum<[96]>;
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def V20 : VR<20, "v20">, DwarfRegNum<[97]>;
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def V21 : VR<21, "v21">, DwarfRegNum<[98]>;
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def V22 : VR<22, "v22">, DwarfRegNum<[99]>;
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def V23 : VR<23, "v23">, DwarfRegNum<[100]>;
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def V24 : VR<24, "v24">, DwarfRegNum<[101]>;
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def V25 : VR<25, "v25">, DwarfRegNum<[102]>;
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def V26 : VR<26, "v26">, DwarfRegNum<[103]>;
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def V27 : VR<27, "v27">, DwarfRegNum<[104]>;
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def V28 : VR<28, "v28">, DwarfRegNum<[105]>;
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def V29 : VR<29, "v29">, DwarfRegNum<[106]>;
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def V30 : VR<30, "v30">, DwarfRegNum<[107]>;
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def V31 : VR<31, "v31">, DwarfRegNum<[108]>;
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def V0 : VR< 0, "v0">, DwarfRegNum<[77, 77]>;
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def V1 : VR< 1, "v1">, DwarfRegNum<[78, 78]>;
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def V2 : VR< 2, "v2">, DwarfRegNum<[79, 79]>;
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def V3 : VR< 3, "v3">, DwarfRegNum<[80, 80]>;
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def V4 : VR< 4, "v4">, DwarfRegNum<[81, 81]>;
|
||||
def V5 : VR< 5, "v5">, DwarfRegNum<[82, 82]>;
|
||||
def V6 : VR< 6, "v6">, DwarfRegNum<[83, 83]>;
|
||||
def V7 : VR< 7, "v7">, DwarfRegNum<[84, 84]>;
|
||||
def V8 : VR< 8, "v8">, DwarfRegNum<[85, 85]>;
|
||||
def V9 : VR< 9, "v9">, DwarfRegNum<[86, 86]>;
|
||||
def V10 : VR<10, "v10">, DwarfRegNum<[87, 87]>;
|
||||
def V11 : VR<11, "v11">, DwarfRegNum<[88, 88]>;
|
||||
def V12 : VR<12, "v12">, DwarfRegNum<[89, 89]>;
|
||||
def V13 : VR<13, "v13">, DwarfRegNum<[90, 90]>;
|
||||
def V14 : VR<14, "v14">, DwarfRegNum<[91, 91]>;
|
||||
def V15 : VR<15, "v15">, DwarfRegNum<[92, 92]>;
|
||||
def V16 : VR<16, "v16">, DwarfRegNum<[93, 93]>;
|
||||
def V17 : VR<17, "v17">, DwarfRegNum<[94, 94]>;
|
||||
def V18 : VR<18, "v18">, DwarfRegNum<[95, 95]>;
|
||||
def V19 : VR<19, "v19">, DwarfRegNum<[96, 96]>;
|
||||
def V20 : VR<20, "v20">, DwarfRegNum<[97, 97]>;
|
||||
def V21 : VR<21, "v21">, DwarfRegNum<[98, 98]>;
|
||||
def V22 : VR<22, "v22">, DwarfRegNum<[99, 99]>;
|
||||
def V23 : VR<23, "v23">, DwarfRegNum<[100, 100]>;
|
||||
def V24 : VR<24, "v24">, DwarfRegNum<[101, 101]>;
|
||||
def V25 : VR<25, "v25">, DwarfRegNum<[102, 102]>;
|
||||
def V26 : VR<26, "v26">, DwarfRegNum<[103, 103]>;
|
||||
def V27 : VR<27, "v27">, DwarfRegNum<[104, 104]>;
|
||||
def V28 : VR<28, "v28">, DwarfRegNum<[105, 105]>;
|
||||
def V29 : VR<29, "v29">, DwarfRegNum<[106, 106]>;
|
||||
def V30 : VR<30, "v30">, DwarfRegNum<[107, 107]>;
|
||||
def V31 : VR<31, "v31">, DwarfRegNum<[108, 108]>;
|
||||
|
||||
// Condition register bits
|
||||
def CR0LT : CRBIT< 0, "0">;
|
||||
|
|
@ -236,24 +236,24 @@ def CR7UN : CRBIT<31, "31">;
|
|||
|
||||
// Condition registers
|
||||
let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
|
||||
def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68]>;
|
||||
def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69]>;
|
||||
def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70]>;
|
||||
def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71]>;
|
||||
def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72]>;
|
||||
def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73]>;
|
||||
def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>;
|
||||
def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>;
|
||||
def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
|
||||
def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
|
||||
def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;
|
||||
def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>;
|
||||
def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
|
||||
def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;
|
||||
def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
|
||||
def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
|
||||
}
|
||||
|
||||
// Link register
|
||||
def LR : SPR<8, "lr">, DwarfRegNum<[65]>;
|
||||
def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
|
||||
//let Aliases = [LR] in
|
||||
def LR8 : SPR<8, "lr">, DwarfRegNum<[65]>;
|
||||
def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
|
||||
|
||||
// Count register
|
||||
def CTR : SPR<9, "ctr">, DwarfRegNum<[66]>;
|
||||
def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>;
|
||||
def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
|
||||
def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
|
||||
|
||||
// VRsave register
|
||||
def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue