forked from OSchip/llvm-project
parent
49beaf40fc
commit
cd018525f8
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@ -94,19 +94,6 @@ more than one use. Itanium will want this too.
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===-------------------------------------------------------------------------===
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int foo(int a, int b) { return a == b ? 16 : 0; }
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_foo:
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cmpw cr7, r3, r4
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mfcr r2
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rlwinm r2, r2, 31, 31, 31
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slwi r3, r2, 4
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blr
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If we exposed the srl & mask ops after the MFCR that we are doing to select
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the correct CR bit, then we could fold the slwi into the rlwinm before it.
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===-------------------------------------------------------------------------===
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#define ARRAY_LENGTH 16
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union bitfield {
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@ -451,16 +438,13 @@ _test:
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cntlzw r2, r2
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cntlzw r3, r3
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srwi r2, r2, 5
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srwi r3, r3, 5
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li r4, 0
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srwi r4, r3, 5
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li r3, 0
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cmpwi cr0, r2, 0
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bne cr0, LBB1_2 ;
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LBB1_1:
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or r4, r3, r3
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or r3, r4, r4
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LBB1_2:
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cmplw cr7, r4, r3
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mfcr r2, 1
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rlwinm r3, r2, 29, 31, 31
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blr
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noticed in 2005-05-11-Popcount-ffs-fls.c.
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