forked from OSchip/llvm-project
GlobalISel: Handle some odd splits in fewerElementsVector
Also add some quick hacks to AMDGPU legality for the tests. llvm-svn: 352591
This commit is contained in:
Matt Arsenault
parent
48dc110eea
commit
ccefbbd0f0
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@ -1441,18 +1441,63 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
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LegalizerHelper::LegalizeResult
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LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy) {
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unsigned Opc = MI.getOpcode();
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned Flags = MI.getFlags();
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unsigned Size = MRI.getType(DstReg).getSizeInBits();
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int NumParts = Size / NarrowSize;
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// FIXME: Don't know how to handle the situation where the small vectors
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// aren't all the same size yet.
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if (Size % NarrowSize != 0)
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const unsigned Opc = MI.getOpcode();
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const unsigned NumOps = MI.getNumOperands() - 1;
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const unsigned NarrowSize = NarrowTy.getSizeInBits();
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const unsigned DstReg = MI.getOperand(0).getReg();
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const unsigned Flags = MI.getFlags();
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const LLT DstTy = MRI.getType(DstReg);
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const unsigned Size = DstTy.getSizeInBits();
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const int NumParts = Size / NarrowSize;
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const LLT EltTy = DstTy.getElementType();
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const unsigned EltSize = EltTy.getSizeInBits();
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const unsigned BitsForNumParts = NarrowSize * NumParts;
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// Check if we have any leftovers. If we do, then only handle the case where
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// the leftover is one element.
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if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
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return UnableToLegalize;
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unsigned NumOps = MI.getNumOperands() - 1;
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if (BitsForNumParts != Size) {
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unsigned AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
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MIRBuilder.buildUndef(AccumDstReg);
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// Handle the pieces which evenly divide into the requested type with
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// extract/op/insert sequence.
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for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
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SmallVector<SrcOp, 4> SrcOps;
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for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
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unsigned PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
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SrcOps.push_back(PartOpReg);
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}
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unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
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unsigned PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
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MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
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AccumDstReg = PartInsertReg;
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Offset += NarrowSize;
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}
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// Handle the remaining element sized leftover piece.
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SmallVector<SrcOp, 4> SrcOps;
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for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
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unsigned PartOpReg = MRI.createGenericVirtualRegister(EltTy);
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MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
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BitsForNumParts);
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SrcOps.push_back(PartOpReg);
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}
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unsigned PartDstReg = MRI.createGenericVirtualRegister(EltTy);
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MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
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MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
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MI.eraseFromParent();
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return Legalized;
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}
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SmallVector<unsigned, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
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@ -140,9 +140,9 @@ body: |
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; CHECK: $vgpr0 = COPY [[COPY4]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s16) = G_TRUNC %0
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%3:_(s16) = G_TRUNC %1
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%4:_(s16) = G_AND %2, %3
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%2:_(s24) = G_TRUNC %0
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%3:_(s24) = G_TRUNC %1
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%4:_(s24) = G_AND %2, %3
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%5:_(s32) = G_ANYEXT %4
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$vgpr0 = COPY %5
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...
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@ -164,6 +164,78 @@ body: |
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_and_v3i32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
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; CHECK-LABEL: name: test_and_v3i32
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; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
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; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV3]]
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV4]]
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; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV5]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
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; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
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%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
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%2:_(<3 x s32>) = G_AND %0, %1
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$vgpr0_vgpr1_vgpr2 = COPY %2
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...
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---
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name: test_and_v4i32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK-LABEL: name: test_and_v4i32
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
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; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV4]]
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV5]]
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; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV6]]
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; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[UV7]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
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%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
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%2:_(<4 x s32>) = G_AND %0, %1
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
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...
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---
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name: test_and_v5i32
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body: |
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bb.0:
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; CHECK-LABEL: name: test_and_v5i32
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; CHECK: [[DEF:%[0-9]+]]:_(<5 x s32>) = G_IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:_(<5 x s32>) = G_IMPLICIT_DEF
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<5 x s32>)
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; CHECK: [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<5 x s32>)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV5]]
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV6]]
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; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV7]]
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; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[UV8]]
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; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[UV9]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32), [[AND4]](s32)
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; CHECK: [[DEF2:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
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; CHECK: [[INSERT:%[0-9]+]]:_(<8 x s32>) = G_INSERT [[DEF2]], [[BUILD_VECTOR]](<5 x s32>), 0
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<8 x s32>)
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%0:_(<5 x s32>) = G_IMPLICIT_DEF
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%1:_(<5 x s32>) = G_IMPLICIT_DEF
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%2:_(<5 x s32>) = G_AND %0, %1
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%3:_(<8 x s32>) = G_IMPLICIT_DEF
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%4:_(<8 x s32>) = G_INSERT %3, %2, 0
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$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %4
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...
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---
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name: test_and_v2s64
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body: |
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