forked from OSchip/llvm-project
[ARM][ReachingDefs] RDA in LoLoops
Add several new methods to ReachingDefAnalysis: - getReachingMIDef, instead of returning an integer, return the MachineInstr that produces the def. - getInstFromId, return a MachineInstr for which the given integer corresponds to. - hasSameReachingDef, return whether two MachineInstr use the same def of a register. - isRegUsedAfter, return whether a register is used after a given MachineInstr. These methods have been used in ARMLowOverhead to replace searching for uses/defs. Differential Revision: https://reviews.llvm.org/D70009
This commit is contained in:
Sam Parker
parent
7047a3a729
commit
cced971fd3
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@ -87,13 +87,29 @@ public:
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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MachineFunctionProperties::Property::NoVRegs).set(
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MachineFunctionProperties::Property::TracksLiveness);
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}
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/// Provides the instruction id of the closest reaching def instruction of
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/// PhysReg that reaches MI, relative to the begining of MI's basic block.
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int getReachingDef(MachineInstr *MI, int PhysReg);
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/// Provides the instruction of the closest reaching def instruction of
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/// PhysReg that reaches MI, relative to the begining of MI's basic block.
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MachineInstr *getReachingMIDef(MachineInstr *MI, int PhysReg);
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/// Provides the MI, from the given block, corresponding to the Id or a
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/// nullptr if the id does not refer to the block.
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MachineInstr *getInstFromId(MachineBasicBlock *MBB, int InstId);
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/// Return whether A and B use the same def of PhysReg.
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bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, int PhysReg);
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/// Return whether the given register is used after MI, whether it's a local
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/// use or a live out.
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bool isRegUsedAfter(MachineInstr *MI, int PhysReg);
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/// Provides the clearance - the number of instructions since the closest
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/// reaching def instuction of PhysReg that reaches MI.
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int getClearance(MachineInstr *MI, MCPhysReg PhysReg);
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@ -6,6 +6,7 @@
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/ReachingDefAnalysis.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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@ -189,7 +190,58 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) {
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return LatestDef;
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}
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MachineInstr* ReachingDefAnalysis::getReachingMIDef(MachineInstr *MI, int PhysReg) {
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return getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg));
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}
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MachineInstr *ReachingDefAnalysis::getInstFromId(MachineBasicBlock *MBB,
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int InstId) {
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assert(MBB->getNumber() < MBBReachingDefs.size() &&
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"Unexpected basic block number.");
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assert(InstId < static_cast<int>(MBB->size()) &&
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"Unexpected instruction id.");
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if (InstId < 0)
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return nullptr;
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for (auto &MI : *MBB) {
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if (InstIds.count(&MI) && InstIds[&MI] == InstId)
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return &MI;
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}
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return nullptr;
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}
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int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) {
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assert(InstIds.count(MI) && "Unexpected machine instuction.");
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return InstIds[MI] - getReachingDef(MI, PhysReg);
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}
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bool ReachingDefAnalysis::hasSameReachingDef(MachineInstr *A, MachineInstr *B,
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int PhysReg) {
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MachineBasicBlock *ParentA = A->getParent();
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MachineBasicBlock *ParentB = B->getParent();
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if (ParentA != ParentB)
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return false;
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return getReachingDef(A, PhysReg) == getReachingDef(B, PhysReg);
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}
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bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI, int PhysReg) {
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MachineBasicBlock *MBB = MI->getParent();
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LivePhysRegs LiveRegs(*TRI);
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LiveRegs.addLiveOuts(*MBB);
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// Yes if the register is live out of the basic block.
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if (LiveRegs.contains(PhysReg))
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return true;
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// Walk backwards through the block to see if the register is live at some
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// point.
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for (auto Last = MBB->rbegin(), End = MBB->rend(); Last != End; ++Last) {
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LiveRegs.stepBackward(*Last);
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if (LiveRegs.contains(PhysReg))
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return InstIds[&*Last] > InstIds[MI];
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}
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return false;
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}
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@ -25,6 +25,8 @@
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ReachingDefAnalysis.h"
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#include "llvm/MC/MCInstrDesc.h"
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using namespace llvm;
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@ -104,10 +106,11 @@ namespace {
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// Is it safe to define LR with DLS/WLS?
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// LR can be defined if it is the operand to start, because it's the same
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// value, or if it's going to be equivalent to the operand to Start.
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MachineInstr *IsSafeToDefineLR();
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MachineInstr *IsSafeToDefineLR(ReachingDefAnalysis *RDA);
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// Check the branch targets are within range and we satisfy our restructi
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void CheckLegality(ARMBasicBlockUtils *BBUtils);
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// Check the branch targets are within range and we satisfy our
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// restrictions.
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void CheckLegality(ARMBasicBlockUtils *BBUtils, ReachingDefAnalysis *RDA);
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bool FoundAllComponents() const {
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return Start && Dec && End;
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@ -127,6 +130,7 @@ namespace {
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class ARMLowOverheadLoops : public MachineFunctionPass {
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MachineFunction *MF = nullptr;
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ReachingDefAnalysis *RDA = nullptr;
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const ARMBaseInstrInfo *TII = nullptr;
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MachineRegisterInfo *MRI = nullptr;
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std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr;
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@ -139,6 +143,7 @@ namespace {
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<ReachingDefAnalysis>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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@ -146,7 +151,8 @@ namespace {
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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MachineFunctionProperties::Property::NoVRegs).set(
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MachineFunctionProperties::Property::TracksLiveness);
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}
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StringRef getPassName() const override {
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@ -183,31 +189,6 @@ static bool IsLoopStart(MachineInstr &MI) {
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MI.getOpcode() == ARM::t2WhileLoopStart;
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}
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template<typename T>
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static MachineInstr* SearchForDef(MachineInstr *Begin, T End, unsigned Reg) {
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for(auto &MI : make_range(T(Begin), End)) {
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for (auto &MO : MI.operands()) {
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if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
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continue;
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return &MI;
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}
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}
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return nullptr;
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}
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static MachineInstr* SearchForUse(MachineInstr *Begin,
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MachineBasicBlock::iterator End,
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unsigned Reg) {
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for(auto &MI : make_range(MachineBasicBlock::iterator(Begin), End)) {
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for (auto &MO : MI.operands()) {
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if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
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continue;
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return &MI;
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}
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}
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return nullptr;
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}
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static bool IsVCTP(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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default:
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@ -221,73 +202,41 @@ static bool IsVCTP(MachineInstr *MI) {
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return false;
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}
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MachineInstr *LowOverheadLoop::IsSafeToDefineLR() {
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auto IsMoveLR = [](MachineInstr *MI, unsigned Reg) {
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return MI->getOpcode() == ARM::tMOVr &&
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MI->getOperand(0).getReg() == ARM::LR &&
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MI->getOperand(1).getReg() == Reg &&
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MI->getOperand(2).getImm() == ARMCC::AL;
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};
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MachineBasicBlock *MBB = Start->getParent();
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unsigned CountReg = Start->getOperand(0).getReg();
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// Walk forward and backward in the block to find the closest instructions
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// that define LR. Then also filter them out if they're not a mov lr.
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MachineInstr *PredLRDef = SearchForDef(Start, MBB->rend(), ARM::LR);
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if (PredLRDef && !IsMoveLR(PredLRDef, CountReg))
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PredLRDef = nullptr;
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MachineInstr *SuccLRDef = SearchForDef(Start, MBB->end(), ARM::LR);
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if (SuccLRDef && !IsMoveLR(SuccLRDef, CountReg))
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SuccLRDef = nullptr;
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// We've either found one, two or none mov lr instructions... Now figure out
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// if they are performing the equilvant mov that the Start instruction will.
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// Do this by scanning forward and backward to see if there's a def of the
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// register holding the count value. If we find a suitable def, return it as
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// the insert point. Later, if InsertPt != Start, then we can remove the
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// redundant instruction.
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if (SuccLRDef) {
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MachineBasicBlock::iterator End(SuccLRDef);
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if (!SearchForDef(Start, End, CountReg)) {
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return SuccLRDef;
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} else
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SuccLRDef = nullptr;
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}
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if (PredLRDef) {
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MachineBasicBlock::reverse_iterator End(PredLRDef);
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if (!SearchForDef(Start, End, CountReg)) {
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return PredLRDef;
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} else
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PredLRDef = nullptr;
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}
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MachineInstr *LowOverheadLoop::IsSafeToDefineLR(ReachingDefAnalysis *RDA) {
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// We can define LR because LR already contains the same value.
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if (Start->getOperand(0).getReg() == ARM::LR)
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return Start;
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unsigned CountReg = Start->getOperand(0).getReg();
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auto IsMoveLR = [&CountReg](MachineInstr *MI) {
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return MI->getOpcode() == ARM::tMOVr &&
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MI->getOperand(0).getReg() == ARM::LR &&
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MI->getOperand(1).getReg() == CountReg &&
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MI->getOperand(2).getImm() == ARMCC::AL;
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};
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MachineBasicBlock *MBB = Start->getParent();
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// Find an insertion point:
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// - Is there a (mov lr, Count) before Start? If so, and nothing else writes
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// to Count before Start, we can insert at that mov.
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// - Is there a (mov lr, Count) after Start? If so, and nothing else writes
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// to Count after Start, we can insert at that mov.
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if (auto *LRDef = RDA->getReachingMIDef(&MBB->back(), ARM::LR)) {
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if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg))
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return LRDef;
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}
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// We've found no suitable LR def and Start doesn't use LR directly. Can we
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// just define LR anyway?
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const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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LivePhysRegs LiveRegs(*TRI);
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LiveRegs.addLiveOuts(*MBB);
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// Not if we've haven't found a suitable mov and LR is live out.
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if (LiveRegs.contains(ARM::LR))
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return nullptr;
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// If LR is not live out, we can insert the instruction if nothing else
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// uses LR after it.
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if (!SearchForUse(Start, MBB->end(), ARM::LR))
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// just define LR anyway?
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if (!RDA->isRegUsedAfter(Start, ARM::LR))
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return Start;
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LLVM_DEBUG(dbgs() << "ARM Loops: Failed to find suitable insertion point for"
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<< " LR\n");
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return nullptr;
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}
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void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils) {
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void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils,
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ReachingDefAnalysis *RDA) {
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if (Revert)
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return;
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@ -320,7 +269,7 @@ void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils) {
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return;
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}
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InsertPt = Revert ? nullptr : IsSafeToDefineLR();
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InsertPt = Revert ? nullptr : IsSafeToDefineLR(RDA);
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if (!InsertPt) {
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LLVM_DEBUG(dbgs() << "ARM Loops: Unable to find safe insertion point.\n");
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Revert = true;
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@ -343,6 +292,7 @@ bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {
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LLVM_DEBUG(dbgs() << "ARM Loops on " << MF->getName() << " ------------- \n");
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auto &MLI = getAnalysis<MachineLoopInfo>();
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RDA = &getAnalysis<ReachingDefAnalysis>();
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MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
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MRI = &MF->getRegInfo();
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TII = static_cast<const ARMBaseInstrInfo*>(ST.getInstrInfo());
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@ -462,7 +412,7 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
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if (!LoLoop.FoundAllComponents())
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return false;
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LoLoop.CheckLegality(BBUtils.get());
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LoLoop.CheckLegality(BBUtils.get(), RDA);
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Expand(LoLoop);
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return true;
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}
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@ -493,19 +443,15 @@ void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
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}
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bool ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI,
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bool AllowFlags) const {
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bool SetFlags) const {
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LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to sub: " << *MI);
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MachineBasicBlock *MBB = MI->getParent();
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// If nothing uses or defines CPSR between LoopDec and LoopEnd, use a t2SUBS.
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bool SetFlags = false;
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if (AllowFlags) {
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if (auto *Def = SearchForDef(MI, MBB->end(), ARM::CPSR)) {
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if (!SearchForUse(MI, MBB->end(), ARM::CPSR) &&
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Def->getOpcode() == ARM::t2LoopEnd)
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SetFlags = true;
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}
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}
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// If nothing defines CPSR between LoopDec and LoopEnd, use a t2SUBS.
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if (SetFlags &&
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(RDA->isRegUsedAfter(MI, ARM::CPSR) ||
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!RDA->hasSameReachingDef(MI, &MBB->back(), ARM::CPSR)))
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SetFlags = false;
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MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
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TII->get(ARM::t2SUBri));
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@ -154,6 +154,7 @@
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; CHECK-NEXT: ARM constant island placement and branch shortening pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: ReachingDefAnalysis
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; CHECK-NEXT: ARM Low Overhead Loops pass
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; CHECK-NEXT: Contiguously Lay Out Funclets
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; CHECK-NEXT: StackMap Liveness Analysis
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@ -0,0 +1,153 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops -verify-machineinstrs %s -o - | FileCheck %s
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# Check that subs isn't used during the revert because there's a def after LoopDec.
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--- |
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define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
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entry:
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%scevgep = getelementptr i32, i32* %q, i32 -1
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%scevgep3 = getelementptr i32, i32* %p, i32 -1
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call void @llvm.set.loop.iterations.i32(i32 %n)
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%limit = lshr i32 %n, 1
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br label %while.body
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while.body: ; preds = %while.body, %entry
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%lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]
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%lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]
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%tmp = phi i32 [ %n, %entry ], [ %tmp2, %while.body ]
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%scevgep7 = getelementptr i32, i32* %lsr.iv, i32 1
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%scevgep4 = getelementptr i32, i32* %lsr.iv4, i32 1
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%tmp1 = load i32, i32* %scevgep7, align 4
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%tmp2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp, i32 1)
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%half = lshr i32 %tmp1, 1
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%cmp = icmp ult i32 %tmp, %limit
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%res = select i1 %cmp, i32 %tmp1, i32 %half
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store i32 %res, i32* %scevgep4, align 4
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%scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
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%scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
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%tmp3 = icmp ne i32 %tmp2, 0
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br i1 %tmp3, label %while.body, label %while.end
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while.end: ; preds = %while.body
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ret i32 0
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}
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; Function Attrs: noduplicate nounwind
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declare void @llvm.set.loop.iterations.i32(i32) #0
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #1
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attributes #0 = { noduplicate nounwind }
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attributes #1 = { nounwind }
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...
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---
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name: do_copy
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
|
||||
cvBytesOfCalleeSavedRegisters: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack: []
|
||||
stack:
|
||||
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
callSites: []
|
||||
constants: []
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: do_copy
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r7, $lr
|
||||
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
; CHECK: $lr = tMOVr killed $r0, 14, $noreg
|
||||
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
|
||||
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
|
||||
; CHECK: renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
|
||||
; CHECK: bb.1.while.body:
|
||||
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
; CHECK: liveins: $lr, $r0, $r1, $r2
|
||||
; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
|
||||
; CHECK: tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
|
||||
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg
|
||||
; CHECK: t2IT 2, 8, implicit-def $itstate
|
||||
; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
|
||||
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
|
||||
; CHECK: t2CMPri renamable $lr, 0, 14, $noreg, implicit-def $cpsr
|
||||
; CHECK: tBcc %bb.1, 4, killed $cpsr
|
||||
; CHECK: tB %bb.2, 14, $noreg
|
||||
; CHECK: bb.2.while.end:
|
||||
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x80000000)
|
||||
liveins: $r0, $r1, $r2, $r7, $lr
|
||||
|
||||
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||||
frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
$lr = tMOVr killed $r0, 14, $noreg
|
||||
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
|
||||
renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
|
||||
renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
|
||||
t2DoLoopStart renamable $lr
|
||||
|
||||
bb.1.while.body:
|
||||
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
liveins: $lr, $r0, $r1, $r2
|
||||
|
||||
renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
|
||||
tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
t2IT 2, 8, implicit-def $itstate
|
||||
renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
|
||||
early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
|
||||
t2CMPri renamable $lr, 0, 14, $noreg, implicit-def $cpsr
|
||||
tBcc %bb.1, 4, killed $cpsr
|
||||
tB %bb.2, 14, $noreg
|
||||
|
||||
bb.2.while.end:
|
||||
$r0, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops -verify-machineinstrs %s -o - | FileCheck %s
|
||||
# Check that subs isn't used during the revert because there's a cpsr use after it.
|
||||
|
||||
--- |
|
||||
define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
|
||||
entry:
|
||||
%scevgep = getelementptr i32, i32* %q, i32 -1
|
||||
%scevgep3 = getelementptr i32, i32* %p, i32 -1
|
||||
call void @llvm.set.loop.iterations.i32(i32 %n)
|
||||
%limit = lshr i32 %n, 1
|
||||
br label %while.body
|
||||
|
||||
while.body: ; preds = %while.body, %entry
|
||||
%lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]
|
||||
%lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]
|
||||
%tmp = phi i32 [ %n, %entry ], [ %tmp2, %while.body ]
|
||||
%scevgep7 = getelementptr i32, i32* %lsr.iv, i32 1
|
||||
%scevgep4 = getelementptr i32, i32* %lsr.iv4, i32 1
|
||||
%tmp1 = load i32, i32* %scevgep7, align 4
|
||||
%tmp2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp, i32 1)
|
||||
%half = lshr i32 %tmp1, 1
|
||||
%cmp = icmp ult i32 %tmp, %limit
|
||||
%res = select i1 %cmp, i32 %tmp1, i32 %half
|
||||
store i32 %res, i32* %scevgep4, align 4
|
||||
%scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
|
||||
%scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
|
||||
%tmp3 = icmp ne i32 %tmp2, 0
|
||||
br i1 %tmp3, label %while.body, label %while.end
|
||||
|
||||
while.end: ; preds = %while.body
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; Function Attrs: noduplicate nounwind
|
||||
declare void @llvm.set.loop.iterations.i32(i32) #0
|
||||
|
||||
; Function Attrs: noduplicate nounwind
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
|
||||
|
||||
; Function Attrs: nounwind
|
||||
declare void @llvm.stackprotector(i8*, i8**) #1
|
||||
|
||||
attributes #0 = { noduplicate nounwind }
|
||||
attributes #1 = { nounwind }
|
||||
|
||||
...
|
||||
---
|
||||
name: do_copy
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
hasWinCFI: false
|
||||
registers: []
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '' }
|
||||
- { reg: '$r1', virtual-reg: '' }
|
||||
- { reg: '$r2', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 8
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 4
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
cvBytesOfCalleeSavedRegisters: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack: []
|
||||
stack:
|
||||
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
callSites: []
|
||||
constants: []
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: do_copy
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r7, $lr
|
||||
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
|
||||
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
|
||||
; CHECK: renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg
|
||||
; CHECK: $lr = tMOVr killed $r0, 14, $noreg
|
||||
; CHECK: bb.1.while.body:
|
||||
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
; CHECK: liveins: $lr, $r0, $r1, $r2
|
||||
; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
|
||||
; CHECK: tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
|
||||
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg
|
||||
; CHECK: t2IT 2, 8, implicit-def $itstate
|
||||
; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
|
||||
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
|
||||
; CHECK: t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
|
||||
; CHECK: tBcc %bb.1, 1, $cpsr
|
||||
; CHECK: tB %bb.2, 14, $noreg
|
||||
; CHECK: bb.2.while.end:
|
||||
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x80000000)
|
||||
liveins: $r0, $r1, $r2, $r7, $lr
|
||||
|
||||
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||||
frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
|
||||
renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
|
||||
t2DoLoopStart renamable $r0
|
||||
renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg
|
||||
$lr = tMOVr killed $r0, 14, $noreg
|
||||
|
||||
bb.1.while.body:
|
||||
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
liveins: $lr, $r0, $r1, $r2
|
||||
|
||||
renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
|
||||
tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
t2IT 2, 8, implicit-def $itstate
|
||||
renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
|
||||
early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
|
||||
t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr
|
||||
tB %bb.2, 14, $noreg
|
||||
|
||||
bb.2.while.end:
|
||||
$r0, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
|
||||
|
||||
...
|
||||
|
|
@ -1,54 +1,89 @@
|
|||
# RUN: llc -mtriple=thumbv7 -start-before=if-converter -o - %s | FileCheck %s
|
||||
# RUN: llc -mtriple=thumbv7 -start-before=if-converter %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
; ModuleID = 'vdup-test.ll'
|
||||
source_filename = "vdup-test.ll"
|
||||
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
|
||||
target triple = "thumbv7"
|
||||
|
||||
define arm_aapcs_vfpcc <2 x i32> @NeonVdupMul(i32 %scalar, i32 %N, <2 x i32> %vector) {
|
||||
entry:
|
||||
%cmp = icmp ne i32 %N, 0
|
||||
%broadcast = insertelement <2 x i32> undef, i32 %scalar, i32 0
|
||||
%dup = shufflevector <2 x i32> %broadcast, <2 x i32> undef, <2 x i32> zeroinitializer
|
||||
%mul = mul <2 x i32> %dup, %vector
|
||||
br i1 %cmp, label %select.end, label %select.false
|
||||
|
||||
select.false: ; preds = %entry
|
||||
br label %select.end
|
||||
|
||||
select.end: ; preds = %entry, %select.false
|
||||
%res = phi <2 x i32> [ %mul, %entry ], [ %vector, %select.false ]
|
||||
ret <2 x i32> %res
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: NeonVdupMul
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
hasWinCFI: false
|
||||
registers: []
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '' }
|
||||
- { reg: '$r1', virtual-reg: '' }
|
||||
- { reg: '$d0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
cvBytesOfCalleeSavedRegisters: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack: []
|
||||
stack: []
|
||||
callSites: []
|
||||
constants: []
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.2, %bb.1
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x50000000), %bb.2(0x30000000)
|
||||
liveins: $d0, $r0, $r1
|
||||
|
||||
t2CMPri killed $r1, 0, 14, $noreg, implicit-def $cpsr
|
||||
|
||||
t2CMPri killed renamable $r1, 0, 14, $noreg, implicit-def $cpsr
|
||||
t2Bcc %bb.2, 0, killed $cpsr
|
||||
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2(0x80000000)
|
||||
liveins: $d0, $r0
|
||||
|
||||
$d16 = VDUP32d killed $r0, 14, $noreg
|
||||
|
||||
renamable $d16 = VDUP32d killed renamable $r0, 14, $noreg
|
||||
; Verify that the neon instructions haven't been conditionalized:
|
||||
; CHECK-LABEL: NeonVdupMul
|
||||
; CHECK: vdup.32
|
||||
; CHECK: vmul.i32
|
||||
$d0 = VMULv2i32 killed $d16, killed $d0, 14, $noreg
|
||||
|
||||
bb.2:
|
||||
renamable $d0 = VMULv2i32 killed renamable $d16, killed renamable $d0, 14, $noreg
|
||||
|
||||
bb.2.select.end:
|
||||
liveins: $d0
|
||||
|
||||
tBX_RET 14, $noreg, implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: NeonVmovVfpLdr
|
||||
body: |
|
||||
bb.0.entry:
|
||||
successors: %bb.1, %bb.2
|
||||
liveins: $r0, $r1
|
||||
|
||||
t2CMPri killed $r1, 0, 14, $noreg, implicit-def $cpsr
|
||||
t2Bcc %bb.2, 1, killed $cpsr
|
||||
|
||||
bb.1:
|
||||
$d0 = VMOVv2i32 0, 14, $noreg
|
||||
tBX_RET 14, $noreg, implicit $d0
|
||||
|
||||
bb.2:
|
||||
liveins: $r0
|
||||
|
||||
$d0 = VLDRD killed $r0, 0, 14, $noreg
|
||||
; Verify that the neon instruction VMOVv2i32 hasn't been conditionalized,
|
||||
; but the VLDR instruction that is available both in the VFP and Advanced
|
||||
; SIMD extensions has.
|
||||
; CHECK-LABEL: NeonVmovVfpLdr
|
||||
; CHECK-DAG: vmov.i32 d0, #0x0
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; CHECK-DAG: vldr{{ne|eq}} d0, [r0]
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|
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tBX_RET 14, $noreg, implicit $d0
|
||||
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue