From ccd7725808fe1a014f8f64e09c4c558ef8084ad8 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Thu, 11 Feb 2016 21:48:32 +0000 Subject: [PATCH] [IRTranslator] Use a single virtual register to represent any Value. PR26161. llvm-svn: 260602 --- .../llvm/CodeGen/GlobalISel/IRTranslator.h | 14 ++++------- llvm/include/llvm/CodeGen/GlobalISel/Types.h | 13 ++++------ llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 24 +++++++++---------- 3 files changed, 21 insertions(+), 30 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h index bc7451340f58..d7414123da2b 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -49,15 +49,11 @@ public: static char ID; private: - // Interface used to lower the everything related to calls. + /// Interface used to lower the everything related to calls. const TargetLowering *TLI; - // Mapping of the values of the current LLVM IR function - // to the related virtual registers. - // We need several virtual registers for the lowering of things - // like structures. Right now, this is just a list of virtual - // registers, but we would need to encapsulate that in a higher - // level class. - ValueToVRegs ValToVRegs; + /// Mapping of the values of the current LLVM IR function + /// to the related virtual registers. + ValueToVReg ValToVReg; // Constants are special because when we encounter one, // we do not know at first where to insert the definition since // this depends on all its uses. @@ -116,7 +112,7 @@ private: void finalize(); /// Get the sequence of VRegs for that \p Val. - const VRegsSequence &getOrCreateVRegs(const Value *Val); + unsigned getOrCreateVReg(const Value *Val); MachineBasicBlock &getOrCreateBB(const BasicBlock *BB); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Types.h b/llvm/include/llvm/CodeGen/GlobalISel/Types.h index 9892a79ad777..879091d3c4d0 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Types.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Types.h @@ -21,16 +21,13 @@ namespace llvm { -typedef SmallVector VRegsSequence; - -/// Map a value to virtual registers. -/// We must support several virtual registers for a value. -/// Indeed each virtual register is mapped to one EVT, but a value -/// may span over several EVT when it is a type representing a structure. -/// In that case the value will be break into EVTs. +/// Map a value to a virtual register. +/// For now, we chose to map aggregate types to on single virtual +/// register. This might be revisited if it turns out to be inefficient. +/// PR26161 tracks that. /// Note: We need to expose this type to the target hooks for thing like /// ABI lowering that would be used during IRTranslation. -typedef DenseMap ValueToVRegs; +typedef DenseMap ValueToVReg; } // End namespace llvm. #endif diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 8b93f4523f2e..ffbda5ba5918 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -30,10 +30,10 @@ char IRTranslator::ID = 0; IRTranslator::IRTranslator() : MachineFunctionPass(ID), MRI(nullptr) { } -const VRegsSequence &IRTranslator::getOrCreateVRegs(const Value *Val) { - VRegsSequence &ValRegSequence = ValToVRegs[Val]; +unsigned IRTranslator::getOrCreateVReg(const Value *Val) { + unsigned &ValReg = ValToVReg[Val]; // Check if this is the first time we see Val. - if (ValRegSequence.empty()) { + if (!ValReg) { // Fill ValRegsSequence with the sequence of registers // we need to concat together to produce the value. assert(Val->getType()->isSized() && @@ -41,12 +41,10 @@ const VRegsSequence &IRTranslator::getOrCreateVRegs(const Value *Val) { assert(!Val->getType()->isAggregateType() && "Not yet implemented"); unsigned Size = Val->getType()->getPrimitiveSizeInBits(); unsigned VReg = MRI->createGenericVirtualRegister(Size); - ValRegSequence.push_back(VReg); + ValReg = VReg; assert(!isa(Val) && "Not yet implemented"); } - assert(ValRegSequence.size() == 1 && - "We support only one vreg per value at the moment"); - return ValRegSequence; + return ValReg; } MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock *BB) { @@ -64,9 +62,9 @@ bool IRTranslator::translateADD(const Instruction &Inst) { // Unless the value is a Constant => loadimm cst? // or inline constant each time? // Creation of a virtual register needs to have a size. - unsigned Op0 = *getOrCreateVRegs(Inst.getOperand(0)).begin(); - unsigned Op1 = *getOrCreateVRegs(Inst.getOperand(1)).begin(); - unsigned Res = *getOrCreateVRegs(&Inst).begin(); + unsigned Op0 = getOrCreateVReg(Inst.getOperand(0)); + unsigned Op1 = getOrCreateVReg(Inst.getOperand(1)); + unsigned Res = getOrCreateVReg(&Inst); MIRBuilder.buildInstr(TargetOpcode::G_ADD, Inst.getType(), Res, Op0, Op1); return true; } @@ -78,7 +76,7 @@ bool IRTranslator::translateReturn(const Instruction &Inst) { // this is not important as a return is the last instruction // of the block anyway. return TLI->LowerReturn(MIRBuilder, Ret, - !Ret ? 0 : *getOrCreateVRegs(Ret).begin()); + !Ret ? 0 : getOrCreateVReg(Ret)); } bool IRTranslator::translate(const Instruction &Inst) { @@ -98,7 +96,7 @@ bool IRTranslator::translate(const Instruction &Inst) { void IRTranslator::finalize() { // Release the memory used by the different maps we // needed during the translation. - ValToVRegs.clear(); + ValToVReg.clear(); Constants.clear(); } @@ -114,7 +112,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &MF) { MIRBuilder.setBasicBlock(MBB); SmallVector VRegArgs; for (const Argument &Arg: F.args()) - VRegArgs.push_back(*getOrCreateVRegs(&Arg).begin()); + VRegArgs.push_back(getOrCreateVReg(&Arg)); bool Succeeded = TLI->LowerFormalArguments(MIRBuilder, F.getArgumentList(), VRegArgs); if (!Succeeded)