forked from OSchip/llvm-project
[x86] add missing tests for fcmp ueq/one
Somehow, the codegen logic for these sequences has gone completely untested until now (note the 2 compare instructions generated per test). There's also an *Intel* AVX optimization opportunity exposed in these cases and the existing tests. Intel's (but not AMD's) AVX spec shows that extra FP predicates were added, so a single comparison should always be sufficient, and operand commutation should never be necessary. llvm-svn: 272397
This commit is contained in:
Sanjay Patel
parent
330a359fb3
commit
cccccd9ab5
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@ -75,6 +75,54 @@ define <4 x i32> @commute_cmpps_uno(<4 x float>* %a0, <4 x float> %a1) {
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_ueq(<4 x float>* %a0, <4 x float> %a1) {
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; SSE-LABEL: commute_cmpps_ueq:
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; SSE: # BB#0:
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; SSE-NEXT: movaps (%rdi), %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: cmpeqps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm1, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_cmpps_ueq:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps (%rdi), %xmm1
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; AVX-NEXT: vcmpeqps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vorps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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%1 = load <4 x float>, <4 x float>* %a0
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%2 = fcmp ueq <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_one(<4 x float>* %a0, <4 x float> %a1) {
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; SSE-LABEL: commute_cmpps_one:
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; SSE: # BB#0:
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; SSE-NEXT: movaps (%rdi), %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: cmpneqps %xmm0, %xmm2
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; SSE-NEXT: cmpordps %xmm1, %xmm0
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; SSE-NEXT: andps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_cmpps_one:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps (%rdi), %xmm1
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; AVX-NEXT: vcmpneqps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpordps %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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%1 = load <4 x float>, <4 x float>* %a0
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%2 = fcmp one <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_lt(<4 x float>* %a0, <4 x float> %a1) {
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; SSE-LABEL: commute_cmpps_lt:
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; SSE: # BB#0:
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@ -187,6 +235,64 @@ define <8 x i32> @commute_cmpps_uno_ymm(<8 x float>* %a0, <8 x float> %a1) {
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_ueq_ymm(<8 x float>* %a0, <8 x float> %a1) {
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; SSE-LABEL: commute_cmpps_ueq_ymm:
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; SSE: # BB#0:
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; SSE-NEXT: movaps (%rdi), %xmm2
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; SSE-NEXT: movaps 16(%rdi), %xmm3
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; SSE-NEXT: movaps %xmm2, %xmm4
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; SSE-NEXT: cmpeqps %xmm0, %xmm4
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; SSE-NEXT: cmpunordps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm4, %xmm0
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; SSE-NEXT: movaps %xmm3, %xmm2
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; SSE-NEXT: cmpeqps %xmm1, %xmm2
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; SSE-NEXT: cmpunordps %xmm3, %xmm1
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; SSE-NEXT: orps %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_cmpps_ueq_ymm:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps (%rdi), %ymm1
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; AVX-NEXT: vcmpeqps %ymm0, %ymm1, %ymm2
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; AVX-NEXT: vcmpunordps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: vorps %ymm2, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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%1 = load <8 x float>, <8 x float>* %a0
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%2 = fcmp ueq <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_one_ymm(<8 x float>* %a0, <8 x float> %a1) {
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; SSE-LABEL: commute_cmpps_one_ymm:
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; SSE: # BB#0:
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; SSE-NEXT: movaps (%rdi), %xmm2
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; SSE-NEXT: movaps 16(%rdi), %xmm3
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; SSE-NEXT: movaps %xmm2, %xmm4
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; SSE-NEXT: cmpneqps %xmm0, %xmm4
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; SSE-NEXT: cmpordps %xmm2, %xmm0
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; SSE-NEXT: andps %xmm4, %xmm0
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; SSE-NEXT: movaps %xmm3, %xmm2
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; SSE-NEXT: cmpneqps %xmm1, %xmm2
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; SSE-NEXT: cmpordps %xmm3, %xmm1
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_cmpps_one_ymm:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps (%rdi), %ymm1
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; AVX-NEXT: vcmpneqps %ymm0, %ymm1, %ymm2
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; AVX-NEXT: vcmpordps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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%1 = load <8 x float>, <8 x float>* %a0
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%2 = fcmp one <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_lt_ymm(<8 x float>* %a0, <8 x float> %a1) {
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; SSE-LABEL: commute_cmpps_lt_ymm:
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; SSE: # BB#0:
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@ -289,6 +395,54 @@ define <2 x i64> @commute_cmppd_ord(<2 x double>* %a0, <2 x double> %a1) {
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_ueq(<2 x double>* %a0, <2 x double> %a1) {
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; SSE-LABEL: commute_cmppd_ueq:
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; SSE: # BB#0:
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; SSE-NEXT: movapd (%rdi), %xmm1
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; SSE-NEXT: movapd %xmm1, %xmm2
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; SSE-NEXT: cmpeqpd %xmm0, %xmm2
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; SSE-NEXT: cmpunordpd %xmm1, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_cmppd_ueq:
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; AVX: # BB#0:
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; AVX-NEXT: vmovapd (%rdi), %xmm1
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; AVX-NEXT: vcmpeqpd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordpd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vorpd %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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%1 = load <2 x double>, <2 x double>* %a0
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%2 = fcmp ueq <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_one(<2 x double>* %a0, <2 x double> %a1) {
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; SSE-LABEL: commute_cmppd_one:
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; SSE: # BB#0:
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; SSE-NEXT: movapd (%rdi), %xmm1
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; SSE-NEXT: movapd %xmm1, %xmm2
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; SSE-NEXT: cmpneqpd %xmm0, %xmm2
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; SSE-NEXT: cmpordpd %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_cmppd_one:
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; AVX: # BB#0:
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; AVX-NEXT: vmovapd (%rdi), %xmm1
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; AVX-NEXT: vcmpneqpd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpordpd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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%1 = load <2 x double>, <2 x double>* %a0
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%2 = fcmp one <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_uno(<2 x double>* %a0, <2 x double> %a1) {
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; SSE-LABEL: commute_cmppd_uno:
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; SSE: # BB#0:
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@ -418,6 +572,64 @@ define <4 x i64> @commute_cmppd_uno_ymmm(<4 x double>* %a0, <4 x double> %a1) {
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_ueq_ymmm(<4 x double>* %a0, <4 x double> %a1) {
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; SSE-LABEL: commute_cmppd_ueq_ymmm:
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; SSE: # BB#0:
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; SSE-NEXT: movapd (%rdi), %xmm2
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; SSE-NEXT: movapd 16(%rdi), %xmm3
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; SSE-NEXT: movapd %xmm2, %xmm4
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; SSE-NEXT: cmpeqpd %xmm0, %xmm4
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; SSE-NEXT: cmpunordpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm4, %xmm0
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; SSE-NEXT: movapd %xmm3, %xmm2
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; SSE-NEXT: cmpeqpd %xmm1, %xmm2
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; SSE-NEXT: cmpunordpd %xmm3, %xmm1
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; SSE-NEXT: orpd %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_cmppd_ueq_ymmm:
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; AVX: # BB#0:
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; AVX-NEXT: vmovapd (%rdi), %ymm1
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; AVX-NEXT: vcmpeqpd %ymm0, %ymm1, %ymm2
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; AVX-NEXT: vcmpunordpd %ymm0, %ymm1, %ymm0
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; AVX-NEXT: vorpd %ymm2, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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%1 = load <4 x double>, <4 x double>* %a0
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%2 = fcmp ueq <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_one_ymmm(<4 x double>* %a0, <4 x double> %a1) {
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; SSE-LABEL: commute_cmppd_one_ymmm:
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; SSE: # BB#0:
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; SSE-NEXT: movapd (%rdi), %xmm2
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; SSE-NEXT: movapd 16(%rdi), %xmm3
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; SSE-NEXT: movapd %xmm2, %xmm4
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; SSE-NEXT: cmpneqpd %xmm0, %xmm4
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; SSE-NEXT: cmpordpd %xmm2, %xmm0
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; SSE-NEXT: andpd %xmm4, %xmm0
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; SSE-NEXT: movapd %xmm3, %xmm2
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; SSE-NEXT: cmpneqpd %xmm1, %xmm2
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; SSE-NEXT: cmpordpd %xmm3, %xmm1
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; SSE-NEXT: andpd %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_cmppd_one_ymmm:
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; AVX: # BB#0:
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; AVX-NEXT: vmovapd (%rdi), %ymm1
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; AVX-NEXT: vcmpneqpd %ymm0, %ymm1, %ymm2
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; AVX-NEXT: vcmpordpd %ymm0, %ymm1, %ymm0
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; AVX-NEXT: vandpd %ymm2, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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%1 = load <4 x double>, <4 x double>* %a0
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%2 = fcmp one <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_lt_ymmm(<4 x double>* %a0, <4 x double> %a1) {
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; SSE-LABEL: commute_cmppd_lt_ymmm:
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; SSE: # BB#0:
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