forked from OSchip/llvm-project
[ARM] Swap cmp operands for automatic shifts
Swap the compare operands if the lhs is a shift and the rhs isn't, as in arm and T2 the shift can be performed by the compare for its second operand. Differential Revision: https://reviews.llvm.org/D39004 llvm-svn: 316562
This commit is contained in:
Sam Parker
parent
6ec2b8ac77
commit
ccb209bb97
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@ -3857,6 +3857,12 @@ SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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break;
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}
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}
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} else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
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(ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
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// In ARM and Thumb-2, the compare instructions can shift their second
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// operand.
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CC = ISD::getSetCCSwappedOperands(CC);
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std::swap(LHS, RHS);
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}
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ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
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@ -0,0 +1,154 @@
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; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
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define i1 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: mov r2, #0
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; CHECK: cmp r0, r1
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; CHECK: movwne r2, #1
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; CHECK: mov r0, r2
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; CHECK-T2: mov{{.*}} r2, #0
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; CHECK-T2: cmp r0, r1
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; CHECK-T2: movne r2, #1
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; CHECK-T2: mov r0, r2
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%tmp = icmp ne i32 %a, %b
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ret i1 %tmp
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}
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define i1 @f2(i32 %a, i32 %b) {
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; CHECK-LABEL: f2:
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; CHECK: mov r2, #0
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; CHECK: cmp r0, r1
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; CHECK: movweq r2, #1
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; CHECK: mov r0, r2
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; CHECK-T2: mov{{.*}} r2, #0
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; CHECK-T2: cmp r0, r1
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; CHECK-T2: moveq r2, #1
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; CHECK-T2: mov r0, r2
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%tmp = icmp eq i32 %a, %b
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ret i1 %tmp
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}
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define i1 @f6(i32 %a, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: mov r2, #0
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; CHECK: cmp {{.*}}, r1, lsl #5
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; CHECK: movweq r2, #1
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; CHECK: mov r0, r2
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; CHECK-T2: mov{{.*}} r2, #0
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; CHECK-T2: cmp.w r0, r1, lsl #5
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; CHECK-T2: moveq r2, #1
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; CHECK-T2: mov r0, r2
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%tmp = shl i32 %b, 5
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%tmp1 = icmp eq i32 %a, %tmp
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ret i1 %tmp1
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}
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define i1 @f7(i32 %a, i32 %b) {
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; CHECK-LABEL: f7:
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; CHECK: mov r2, #0
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; CHECK: cmp r0, r1, lsr #6
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; CHECK: movwne r2, #1
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; CHECK: mov r0, r2
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; CHECK-T2: mov{{.*}} r2, #0
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; CHECK-T2: cmp.w r0, r1, lsr #6
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; CHECK-T2: movne r2, #1
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; CHECK-T2: mov r0, r2
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%tmp = lshr i32 %b, 6
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%tmp1 = icmp ne i32 %a, %tmp
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ret i1 %tmp1
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}
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define i1 @f8(i32 %a, i32 %b) {
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; CHECK-LABEL: f8:
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; CHECK: mov r2, #0
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; CHECK: cmp r0, r1, asr #7
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; CHECK: movweq r2, #1
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; CHECK: mov r0, r2
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; CHECK-T2: mov{{.*}} r2, #0
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; CHECK-T2: cmp.w r0, r1, asr #7
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; CHECK-T2: moveq r2, #1
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; CHECK-T2: mov r0, r2
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%tmp = ashr i32 %b, 7
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%tmp1 = icmp eq i32 %a, %tmp
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ret i1 %tmp1
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}
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define i1 @f9(i32 %a) {
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; CHECK-LABEL: f9:
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; CHECK: mov r1, #0
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; CHECK: cmp r0, r0, ror #8
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; CHECK: movwne r1, #1
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; CHECK: mov r0, r1
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; CHECK-T2: mov{{.*}} r1, #0
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; CHECK-T2: cmp.w r0, r0, ror #8
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; CHECK-T2: movne r1, #1
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; CHECK-T2: mov r0, r1
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%l8 = shl i32 %a, 24
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%r8 = lshr i32 %a, 8
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%tmp = or i32 %l8, %r8
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%tmp1 = icmp ne i32 %a, %tmp
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ret i1 %tmp1
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}
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; CHECK-LABEL: swap_cmp_shl
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; CHECK: mov r2, #0
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; CHECK: cmp r1, r0, lsl #11
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; CHECK: movwlt r2, #1
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; CHECK-T2: mov{{.*}} r2, #0
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; CHECK-T2: cmp.w r1, r0, lsl #11
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; CHECK-T2: movlt r2, #1
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define arm_aapcscc i32 @swap_cmp_shl(i32 %a, i32 %b) {
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entry:
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%shift = shl i32 %a, 11
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%cmp = icmp sgt i32 %shift, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; CHECK-LABEL: swap_cmp_lshr
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; CHECK: mov r2, #0
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; CHECK: cmp r1, r0, lsr #11
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; CHECK: movwhi r2, #1
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; CHECK-T2: mov{{.*}} r2, #0
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; CHECK-T2: cmp.w r1, r0, lsr #11
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; CHECK-T2: movhi r2, #1
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define arm_aapcscc i32 @swap_cmp_lshr(i32 %a, i32 %b) {
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entry:
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%shift = lshr i32 %a, 11
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%cmp = icmp ult i32 %shift, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; CHECK-LABEL: swap_cmp_ashr
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; CHECK: mov r2, #0
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; CHECK: cmp r1, r0, asr #11
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; CHECK: movwle r2, #1
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; CHECK-T2: mov{{.*}} r2, #0
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; CHECK-T2: cmp.w r1, r0, asr #11
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; CHECK-T2: movle r2, #1
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define arm_aapcscc i32 @swap_cmp_ashr(i32 %a, i32 %b) {
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entry:
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%shift = ashr i32 %a, 11
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%cmp = icmp sge i32 %shift, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; CHECK-LABEL: swap_cmp_rotr
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; CHECK: mov r2, #0
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; CHECK: cmp r1, r0, ror #11
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; CHECK: movwls r2, #1
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; CHECK-T2: mov{{.*}} r2, #0
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; CHECK-T2: cmp.w r1, r0, ror #11
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; CHECK-T2: movls r2, #1
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define arm_aapcscc i32 @swap_cmp_rotr(i32 %a, i32 %b) {
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entry:
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%lsr = lshr i32 %a, 11
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%lsl = shl i32 %a, 21
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%ror = or i32 %lsr, %lsl
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%cmp = icmp uge i32 %ror, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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@ -1,52 +0,0 @@
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; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
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; These tests would be improved by 'movs r0, #0' being rematerialized below the
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; test as 'mov.w r0, #0'.
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define i1 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: cmp {{.*}}, r1
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%tmp = icmp ne i32 %a, %b
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ret i1 %tmp
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}
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define i1 @f2(i32 %a, i32 %b) {
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; CHECK-LABEL: f2:
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; CHECK: cmp {{.*}}, r1
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%tmp = icmp eq i32 %a, %b
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ret i1 %tmp
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}
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define i1 @f6(i32 %a, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: cmp.w {{.*}}, r1, lsl #5
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%tmp = shl i32 %b, 5
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%tmp1 = icmp eq i32 %tmp, %a
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ret i1 %tmp1
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}
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define i1 @f7(i32 %a, i32 %b) {
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; CHECK-LABEL: f7:
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; CHECK: cmp.w {{.*}}, r1, lsr #6
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%tmp = lshr i32 %b, 6
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%tmp1 = icmp ne i32 %tmp, %a
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ret i1 %tmp1
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}
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define i1 @f8(i32 %a, i32 %b) {
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; CHECK-LABEL: f8:
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; CHECK: cmp.w {{.*}}, r1, asr #7
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%tmp = ashr i32 %b, 7
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%tmp1 = icmp eq i32 %a, %tmp
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ret i1 %tmp1
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}
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define i1 @f9(i32 %a, i32 %b) {
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; CHECK-LABEL: f9:
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; CHECK: cmp.w {{.*}}, {{.*}}, ror #8
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%l8 = shl i32 %a, 24
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%r8 = lshr i32 %a, 8
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%tmp = or i32 %l8, %r8
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%tmp1 = icmp ne i32 %a, %tmp
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ret i1 %tmp1
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}
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