forked from OSchip/llvm-project
[mips][microMIPSr6] Implement SUB and SUBU instructions
Differential Revision: http://reviews.llvm.org/D8764 llvm-svn: 236118
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@ -24,6 +24,8 @@ class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
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class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
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class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
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class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
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class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
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class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
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//===----------------------------------------------------------------------===//
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//
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@ -48,6 +50,8 @@ class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
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list<Register> Defs = [RA];
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}
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class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
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class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
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class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
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class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm> {
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@ -87,4 +91,6 @@ def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
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def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
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def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
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def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
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}
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@ -20,3 +20,8 @@
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# CHECK: pref 1, 8($5)
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0x60 0x25 0x20 0x08
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0x00 0xa4 0x19 0x90 # CHECK: sub $3, $4, $5
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0x00 0xa4 0x19 0xd0 # CHECK: subu $3, $4, $5
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@ -9,3 +9,6 @@
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bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c]
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cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
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pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
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sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90]
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subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]
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