forked from OSchip/llvm-project
[mips] Fix the predicates of jump and branch and link instructions
Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46114 llvm-svn: 331175
This commit is contained in:
Simon Dardis
parent
deb01ea126
commit
cc95a9c557
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@ -948,45 +948,53 @@ let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeJumpTargetMM" in
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J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
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IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
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let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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let DecoderNamespace = "MicroMips" in {
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let DecoderMethod = "DecodeJumpTargetMM" in {
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def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
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def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
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def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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}
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def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
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def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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/// Jump Instructions - Short Delay Slot
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def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
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def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
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def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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/// Branch Instructions
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def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
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BEQ_FM_MM<0x25>;
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BEQ_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
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BEQ_FM_MM<0x2d>;
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BEQ_FM_MM<0x2d>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
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BGEZ_FM_MM<0x2>;
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BGEZ_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
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BGEZ_FM_MM<0x6>;
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BGEZ_FM_MM<0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
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BGEZ_FM_MM<0x4>;
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BGEZ_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
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BGEZ_FM_MM<0x0>;
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BGEZ_FM_MM<0x0>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
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BGEZAL_FM_MM<0x03>;
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BGEZAL_FM_MM<0x03>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
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BGEZAL_FM_MM<0x01>;
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BGEZAL_FM_MM<0x01>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BAL_BR_MM : BAL_BR_Pseudo<BGEZAL_MM, brtarget_mm>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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/// Branch Instructions - Short Delay Slot
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def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
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GPR32Opnd>, BGEZAL_FM_MM<0x13>;
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GPR32Opnd>, BGEZAL_FM_MM<0x13>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
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GPR32Opnd>, BGEZAL_FM_MM<0x11>;
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}
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def B_MM : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch, ISA_MICROMIPS;
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let DecoderNamespace = "MicroMips" in {
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GPR32Opnd>, BGEZAL_FM_MM<0x11>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def B_MM : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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/// Control Instructions
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def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM, ISA_MICROMIPS;
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@ -1213,7 +1221,7 @@ def : MipsPat<(atomic_load_16 addr:$a),
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(LH_MM addr:$a)>;
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defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
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SLTiu_MM, ZERO>;
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SLTiu_MM, ZERO>, ISA_MICROMIPS32_NOT_MIPS32R6;
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defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
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defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
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@ -1323,6 +1331,8 @@ let Predicates = [InMicroMips] in {
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def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;
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def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,
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ISA_MICROMIPS;
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def : MipsInstAlias<"bal $offset", (BGEZAL_MM ZERO, brtarget_mm:$offset), 1>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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}
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def : MipsInstAlias<"hypcall", (HYPCALL_MM 0), 1>,
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ISA_MICROMIPS32R5, ASE_VIRT;
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@ -1649,9 +1649,9 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
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PseudoInstExpansion<(JumpInst RO:$rs)>;
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}
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class BAL_BR_Pseudo<Instruction RealInst> :
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PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
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PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
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class BAL_BR_Pseudo<Instruction RealInst, DAGOperand opnd> :
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PseudoSE<(outs), (ins opnd:$offset), [], II_BCCZAL>,
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PseudoInstExpansion<(RealInst ZERO, opnd:$offset)> {
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let isBranch = 1;
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let isTerminator = 1;
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let isBarrier = 1;
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@ -2146,54 +2146,61 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_32, ISA_MIPS2_NOT_32R6_64R6;
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def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6;
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}
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/// Jump and Branch Instructions
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let AdditionalPredicates = [NotInMicroMips, RelocNotPIC] in
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def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
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AdditionalRequires<[RelocNotPIC, NotInMicroMips]>, IsBranch;
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IsBranch, ISA_MIPS1;
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let AdditionalPredicates = [NotInMicroMips] in {
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def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
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def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
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def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>,
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ISA_MIPS1;
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def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
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BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
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def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
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def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>,
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ISA_MIPS1;
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def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>,
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BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
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def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
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BGEZ_FM<1, 1>;
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BGEZ_FM<1, 1>, ISA_MIPS1;
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def BGEZL : MMRel, CBranchZeroLikely<"bgezl", brtarget, GPR32Opnd>,
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BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
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def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
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BGEZ_FM<7, 0>;
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BGEZ_FM<7, 0>, ISA_MIPS1;
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def BGTZL : MMRel, CBranchZeroLikely<"bgtzl", brtarget, GPR32Opnd>,
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BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
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def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
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BGEZ_FM<6, 0>;
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BGEZ_FM<6, 0>, ISA_MIPS1;
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def BLEZL : MMRel, CBranchZeroLikely<"blezl", brtarget, GPR32Opnd>,
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BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
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def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
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BGEZ_FM<1, 0>;
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BGEZ_FM<1, 0>, ISA_MIPS1;
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def BLTZL : MMRel, CBranchZeroLikely<"bltzl", brtarget, GPR32Opnd>,
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BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
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def B : UncondBranch<BEQ, brtarget>,
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AdditionalRequires<[NotInMicroMips]>;
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def B : UncondBranch<BEQ, brtarget>, ISA_MIPS1;
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def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>, ISA_MIPS1;
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def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
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let AdditionalPredicates = [NotInMicroMips, NoIndirectJumpGuards] in {
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def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
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def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
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}
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def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
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ISA_MIPS32_NOT_32R6_64R6;
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def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
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ISA_MIPS1_NOT_32R6_64R6;
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def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>,
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BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
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def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
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ISA_MIPS1_NOT_32R6_64R6;
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def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,
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BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
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def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
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let AdditionalPredicates = [NotInMicroMips, NoIndirectJumpGuards] in {
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def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM, ISA_MIPS1;
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def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>, ISA_MIPS1;
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
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ISA_MIPS32_NOT_32R6_64R6;
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def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
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ISA_MIPS1_NOT_32R6_64R6;
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def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>,
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BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
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def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
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ISA_MIPS1_NOT_32R6_64R6;
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def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,
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BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
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def BAL_BR : BAL_BR_Pseudo<BGEZAL, brtarget>;
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}
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let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in {
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def TAILCALL : TailCall<J, jmptarget>;
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}
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@ -285,7 +285,7 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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const unsigned BalOp =
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Subtarget.hasMips32r6()
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? Subtarget.inMicroMipsMode() ? Mips::BALC_MMR6 : Mips::BALC
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: Mips::BAL_BR;
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: Subtarget.inMicroMipsMode() ? Mips::BAL_BR_MM : Mips::BAL_BR;
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if (!ABI.IsN64()) {
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// Pre R6:
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@ -5,7 +5,7 @@
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; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMM
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; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PICMM
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; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMMR6
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; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC
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; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PICMMR6
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@ -22,5 +22,6 @@ bosco: ; preds = %bosco, %entry
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; STATIC: j $BB0_1 # <MCInst #{{.*}} J
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; STATICMM: j $BB0_1 # <MCInst #{{.*}} J_MM
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; STATICMMR6: bc $BB0_1 # <MCInst #{{.*}} BC_MMR6
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; PICMMR6: bc $BB0_1 # <MCInst #{{.*}} BC_MMR6
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; PIC16: b $BB0_1
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; STATIC16: b $BB0_1
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